Table 283. Rom1 Table; Table 284. Rom2 Table - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
38.13 CPU2 ROM tables
The ROM tables are CoreSight components that contain the base addresses of all the
CoreSight debug components accessible via the AHBD. These tables allow a debugger to
discover the topology of the CoreSight system automatically.
There are two ROM tables in the CPU2 sub-system:
•
ROM1: CPU2 processor ROM table, pointed to by the AP_BASER register in the CPU2
AHB-AP. It contains the base address pointers for the CTI, as well as for the CPU2
ROM table.
•
ROM2: CPU2 ROM table, containing pointers to the CPU2 system control space (SCS)
registers, which allow the debugger to identify the CPU core, as well as the remaining
CoreSight components in the CPU2 subsystem (PBU, DWT).
ROM1 occupies a 4-Kbyte, 32-bit wide chunk of AHB address space, from 0xF0000000 to
0xF0000FFC.
Address in ROM
Component name
table
0xF0000000 CPU2 ROM table
0xF0000004
0xF0000008
0xF000000C
0xF0000010
0xF000000C to
0xF0000FC8
0xF0000FCC to
ROM table registers
0xF0000FFC
ROM2 occupies a 4-Kbyte, 32-bit wide chunk of APB-D address space, from 0xE00FF000
to 0xE00FFFFC.
Address in ROM
table
0xE00FF000
0xE00FF004
0xE00FF008
0xE00FF00C
0xE00FF010 to
0xE00FFFC8
0xE00FFFCC to
0xE00FFFFC

Table 283. ROM1 table

Component base
0xE00FF000
CTI 0xF0001000
Not used
Not used
Top of table
Reserved

Table 284. ROM2 table

Component Component base
name address
SCS 0xE000E000
DWT 0xE0001000
BPU 0xE0002000
Top of table
Reserved
ROM table
registers
Component
address address offset
0xF00FF000
0x00001000
-
-
-
-
-
Component
address offset
0xFFF0F000
0xFFF02000
0xFFF03000
-
-
-
RM0453 Rev 5
Debug support (DBG)
Size
4 KB
4 KB
- -
- -
- -
- -
- -
Size
4 KB
4 KB
4 KB
- -
- -
- -
Entry
0xF00FF003
0x00001003
0x00002002
0x10000002
0x00000000
0x00000000
See Table 285
Entry
0xFFF0F003
0xFFF02003
0xFFF03003
0x00000000
0x00000000
See Table 286
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