Table 273. Cpu2 Cti Outputs; Table 274. Cpu1 Cti Inputs; Table 275. Cpu1 Cti Outputs - STMicroelectronics STM32WL5 Series Reference Manual

Debug support (DBG)
No.
2
3
4
5
6
7
No. Output signal Destination component
0
1
2
3
4
5
6
7 DBGRESTART
No. Source signal
0
1
2
3
4
5
6
7
No. Source signal
0
1
2
1352/1450
Table 272. CPU2 CTI inputs (continued)
Source signal Source component
-
-
-
-
-
-
EDBGRQ
-
-
-
-
-
-
Source component
HALTED
-
-
-
-
-
-
-
Source component
EDBGRQ
-
-
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used

Table 273. CPU2 CTI outputs

CPU2 CPU2 halt request - Puts CPU2 in debug mode.
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
CPU2 CPU2 restart request - CPU2 exits debug mode.

Table 274. CPU1 CTI inputs

CPU1 CPU1 halted - indicates CPU1 is in debug mode.
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used
- Not used

Table 275. CPU1 CTI outputs

CPU1 CPU1 halt request - Puts CPU1 in debug mode.
- Not used
- Not used
RM0453 Rev 5
RM0453
Comments
Comments
Comments
Comments