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RM0453
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ETRSEL[1:0]
Res.
Res.
rw
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: ETR source selection
Bits 13:0 Reserved, must be kept at reset value.
26.4.24
TIM2 timer input selection register (TIM2_TISEL)
Address offset: 0x68
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:8 TI2SEL[3:0]: TI2[0] to TI2[15] input selection
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: TI1[0] to TI1[15] input selection
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits select the ETR input source.
0000: GPIO or LSE internal clock, as per ETR_RMP bit in TIM2_OR1
0001: COMP1
0010: COMP2
Others: Reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
TI2SEL[3:0]
rw
rw
rw
These bits select the TI2[0] to TI2[15] input source.
0000: TIM2_CH2 input
Others: Reserved
These bits select the TI1[0] to TI1[15] input source.
0000: TIM2_CH1 input
Others: Reserved
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
rw
RM0453 Rev 5
General-purpose timer (TIM2)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
TI1SEL[3:0]
rw
rw
17
16
ETRSEL[3:2]
rw
rw
1
0
Res.
Res.
17
16
Res.
Res.
1
0
rw
rw
889/1450
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