Table 141. Processing Latency For Gcm And Ccm (In Clock Cycles) - STMicroelectronics STM32WL5 Series Reference Manual

RM0453

Table 141. Processing latency for GCM and CCM (in clock cycles)

Key size Mode of operation
Mode 1: Encryption/
128-bit
Mode 3: Decryption
Mode 1: Encryption/
256-bit
Mode 3: Decryption
1. Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle).
23.7 AES registers
23.7.1 AES control register (AES_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. GCMPH[1:0]
rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 NPBLB[3:0]: Number of padding bytes in last block
The bitfield sets the number of padding bytes in last block of payload:
0000: All bytes are valid (no padding)
0001: Padding for one least-significant byte of last block
...
1111: Padding for 15 least-significant bytes of last block
Bit 19 Reserved, must be kept at reset value.
Bit 18 KEYSIZE: Key size selection
This bitfield defines the length of the key used in the AES cryptographic core, in bits:
0: 128
1: 256
Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write
access and it is not cleared by that write access.
Bit 17 Reserved, must be kept at reset value.
Bit 15 Reserved, must be kept at reset value.
Algorithm
GCM
CCM
GCM
CCM
28 27 26 25
Res. Res. Res.
12 11 10 9
ERRIE CCFIE
rw rw rw rw
Init Phase
phase
64
63
88
87
24 23 22
Res. NPBLB[3:0]
rw rw
8 7 6
ERRC CCFC CHMOD[1:0]
rw rw rw
RM0453 Rev 5
AES hardware accelerator (AES)
Header Payload
(1) (1)
phase
35 51
55 114
35 75
79 162
21 20 19 18
Res.
rw rw rw
5 4 3 2
MODE[1:0] DATATYPE[1:0]
rw rw rw rw
(1)
Tag phase
59
58
75
82
17 16
Res.
rw
1 0
EN
rw rw
683/1450
694