ST STM32G4 Series Reference Manual page 1519

RM0440
Bit 2 WUTWF: Wakeup timer write flag
Bit 1 ALRBWF: Alarm B write flag
Bit 0 ALRAWF: Alarm A write flag
34.6.5 RTC prescaler register (RTC_PRER)
This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to
page 1506.
This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x10
Backup domain reset value: 0x007F 00FF
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res.
rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
This bit is set by hardware when WUT value can be changed, after the WUTE bit has been
set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Wakeup timer configuration update not allowed except in initialization mode
1: Wakeup timer configuration update allowed
This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm B update not allowed
1: Alarm B update allowed
This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm A update not allowed
1: Alarm A update allowed
1506.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
Calendar initialization and configuration on
24 23 22
Res. Res.
rw
8 7 6
PREDIV_S[14:0]
rw rw rw
RM0440 Rev 1
Real-time clock (RTC)
RTC register
21 20 19 18
PREDIV_A[6:0]
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
1519/2083
1551