ST STM32G4 Series Reference Manual page 1520

Real-time clock (RTC)
34.6.6 RTC wakeup timer register (RTC_WUTR)
This register can be written only when WUTWF is set to 1 in RTC_ICSR.
This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x14
Backup domain reset value: 0x0000 FFFF
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
34.6.7 RTC control register (RTC_CR)
This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x18
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
TAMP TAMP
OUT2
ALRM_ ALRM_ Res.
EN
TYPE PU
rw rw rw
15 14 13
ALRB ALRA
TSIE WUTIE
IE
rw rw rw
1520/2083
1506.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every
(WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits
of the RTC_CR register.
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE
is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.
1506.
28 27 26 25
TAMP TAMP
Res.
OE TS
rw rw
12 11 10 9
TSE WUTE ALRBE ALRAE
IE
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
WUT[15:0]
rw rw rw
24 23 22
ITSE COE OSEL[1:0]
rw rw rw
8 7 6
Res. FMT
SHAD
rw rw
RM0440 Rev 1
RTC register
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
RTC register
21 20 19 18
POL COSEL BKP
rw rw rw rw
5 4 3 2
BYP REFCK TS
ON EDGE
rw rw rw rw
RM0440
17 16
Res. Res.
1 0
rw rw
17 16
SUB1H ADD1H
w w
1 0
WUCKSEL[2:0]
rw rw