Reserved Sr Bits— Bits 10–14; Loop Flag (Lf)—Bit 15; Operating Mode Register; Table 5-1 Interrupt Mask Bit Definition - Motorola DSP56800 Manual

I1 I0
0 0
0 1
1 0
1 1
5.1.8.10 Reserved SR Bits— Bits 10–14
The reserved SR bits 10–14 are reserved for future expansion and will read as zero during DSP read
operations. These bits should be written with zero for future compatibility.
5.1.8.11 Loop Flag (LF)—Bit 15
The loop flag (LF) bit (SR bit 15) is set when a program loop is in progress and enables the detection of the
end of a program loop. The LF bit is the only SR bit that is restored when terminating a program loop.
Stacking and restoring the LF when initiating and exiting a program loop, respectively, allows the nesting
of program loops; see Section 5.1.9.7, "Nested Looping Bit (NL)—Bit 15." REP looping does not affect
this bit. The LF is cleared during processor reset.
The LF is not cleared at the start of an interrupt service routine. This differs
from the DSP56100 Family, where this bit is cleared upon entering an
interrupt service routine. This will not cause a problem as long as the
interrupt service routine code does not fetch the instruction whose address
is stored in the LA register. This is typically the case because usually the
interrupt service routine is located in a separate portion of program
memory.
This bit should never be explicitly cleared by a MOVE or bit-field
instruction when the NL bit in the OMR register is set to a one.
The LF bit is also affected by any accesses to the hardware stack register. Any move instruction that writes
this register copies the old contents of the LF bit into the NL bit and then sets the LF bit. Any reads of this
register, such as from a MOVE or TSTW instruction, copy the NL bit into the LF bit and then clear the NL
bit.
5.1.9

Operating Mode Register

The operating mode register (OMR) is a 16-bit register that defines the current chip operating mode of the
processor. The OMR bits are affected by processor reset, operations on the HWS, and instructions that
directly reference the OMR. A DO loop will also affect the OMR, specifically the NL bit.
During processor reset, the chip operating mode bits will be loaded from the external mode select pins. The
operating mode register format is shown in Figure 5-5 on page 5-10 and is described in the subsequent
discussion.
Table 5-1. Interrupt Mask Bit Definition
Exceptions Permitted
(Reserved)
IPL 0, 1
(Reserved)
IPL 1
NOTE:
Program Controller
Architecture and Programming Model
Exceptions Masked
(Reserved)
None
(Reserved)
IPL 0
5-9