Transfer Request Generation - Motorola MC68302 User Manual

Integrated multi-protocol processor
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When operating in a 16-bit bus environment with an 8-bit peripheral, the
peripheral may be placed on one-half of the bus (consecutive even or odd
addresses only). In this case, SSIZE (or DSIZE) must be set to 16 bit, and the
IDMA will perform data packing. If the 8-bit peripheral is to be arranged with
consecutive addresses, both SSIZE and DSIZE must be 8 bit. As a result, the
peripheral's addresses must be incremented twice after each peripheral bus
cycle, which results in adding four to the address for each data transfer (two
cycles per transfer). This is consistent with the M68000 MOVEP instruction.
Refer to Table 3-1 to see how the SAPR and DAPR will be incremented in all
combinations.
Table 3-1. SAPR and DAPR Incrementing Rules
Bus
Source
Destination
SAPR
DAPR
Transfer
Width
Size
Size
Increment
Increment
Description
8 Bit
x
x
+1
+1
Read Byte - Write Byte
Packing is Not Possible
16 Bit
Byte
Byte
+1
+1
Read Byte - Write Byte
Packing is Not Desired
16 Bit
Byte
Word
+4
+2
Read Byte, Read Byte -
Write Word
Operand Packing
16 Bit
Word
Byte
+2
+4
Read Word - Write Byte,
Write Byte
Operand Unpacking
16 Bit
Word
Word
+2
+2
Read Word - Write Word
3.1.4.4 TRANSFER REQUEST GENERATION.
IDMA transfers may be initiated by
either internally or externally generated requests. Internally generated re-
quests can be initiated by setting STA in the CMR. Externally generated
transfers are those requested by an external device using OREO in conjunc-
tion with the activation of STA.
3-12
Internal Maximum Rate
The first method of internal request generation is a nonstop transfer until
the transfer count is exhausted. If this method is chosen, the IDMA will
arbitrate for the bus and begin transferring data after STA is set and the
IDMA becomes the bus master. If no exception occurs, all operands in the
data block will be transferred in one burst with the IDMA using 100 percent
of the available bus bandwidth (unless an external bus master requests
the bus or the M68000 core has an unmasked pending interrupt request
and BCLM
=
1 ). See 3.1.6 OMA Bus Arbitration for more details.
MC68302 USER'S MANUAL
MOTOROLA

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