Mpc8240 Integrated Processor Features - Motorola MPC8240 User Manual

memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power
management features. The integration reduces the overall packaging requirements and the
number of discrete devices required for an embedded system.
The MPC8240 contains an internal peripheral logic bus that interfaces the processor core
to the peripheral logic. The core can operate at a variety of frequencies, allowing the
designer to trade off performance for power consumption. The processor core is clocked
from a separate PLL, which is referenced to the peripheral logic PLL. This allows the
microprocessor and the peripheral logic block to operate at different frequencies, while
maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus
(depending on memory data bus width) and a 32-bit address bus along with control signals
that enable the interface between the processor and peripheral logic to be optimized for
performance. PCI accesses to the MPC8240's memory space are passed to the processor
bus for snooping when snoop mode is enabled.
The processor core and peripheral logic are general-purpose in order to serve a variety of
embedded applications. The MPC8240 can be used as either a PCI host or PCI agent
controller.

1.1.1 MPC8240 Integrated Processor Features

This section summarizes the features of the MPC8240. Major features of the MPC8240 are
as follows:
• Peripheral logic
— Memory interface
– Programmable timing supporting either FPM DRAM, EDO DRAM or
SDRAM
– High-bandwidth bus (32-/64-bit data bus) to DRAM
– Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices
– Supports 1-Mbyte to 1-Gbyte DRAM memory
– 16 Mbytes of ROM space
– 8-, 32-, or 64-bit ROM
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
– Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller
interface with programmable address strobe timing
— 32-bit PCI interface operating up to 66 MHz
– PCI 2.1-compliant
MPC8240 Integrated Processor Overview
Chapter 1. Overview 1-3