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2.1.5.8 C Status Bit
The C bit is set when a carry occurs during addition or a borrow occurs during subtrac-
tion. The C bit also acts as an error flag for multiply and divide operations. Shift and
rotate instructions operate through the C bit to facilitate multiple-word shifts.
2.2 Data Types
The CPU12 uses the following types of data:
•
Bits
•
5-bit signed integers
•
8-bit signed and unsigned integers
•
8-bit, 2-digit binary coded decimal numbers
•
9-bit signed integers
•
16-bit signed and unsigned integers
•
16-bit effective addresses
•
32-bit signed and unsigned integers
Negative integers are represented in two's complement form.
Five-bit and 9-bit signed integers are used only as offsets for indexed addressing
modes.
Sixteen-bit effective addresses are formed during addressing mode computations.
Thirty-two-bit integer dividends are used by extended division instructions. Extended
multiply and extended multiply-and-accumulate instructions produce 32-bit products.
2.3 Memory Organization
The standard CPU12 address space is 64 Kbytes. Some M68HC12 devices support
a paged memory expansion scheme that increases the standard space by means of
predefined windows in address space. The CPU12 has special instructions that sup-
port use of expanded memory. See
formation.
Eight-bit values can be stored at any odd or even byte address in available memory.
Sixteen-bit values are stored in memory as two consecutive bytes; the high byte occu-
pies the lowest address, but need not be aligned to an even boundary. Thirty-two-bit
values are stored in memory as four consecutive bytes; the high byte occupies the low-
est address, but need not be aligned to an even boundary.
All I/O and all on-chip peripherals are memory-mapped. No special instruction syntax
is required to access these addresses. On-chip registers and memory are typically
grouped in blocks which can be relocated within the standard 64-Kbyte address
space. Refer to device documentation for specific information.
2.4 Instruction Queue
The CPU12 uses an instruction queue to buffer program information. The mechanism
is called a queue rather than a pipeline because a typical pipelined CPU executes
more than one instruction at the same time, while the CPU12 always finishes execut-
ing an instruction before beginning to execute another. Refer to
STRUCTION QUEUE
CPU12
REFERENCE MANUAL
SECTION 10 MEMORY EXPANSION
for more information.
OVERVIEW
for more in-
SECTION 4 IN-
MOTOROLA
2-5
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