Mc68328 Architecture; Ec000 Static Core; Ec000 Core Programming Model; Data Types And Address Modes - Motorola DragonBall MC68328 User Manual

Overview
essential signals are brought out to pins. The primary package is the surface-mount plastic
QFP for the smallest possible footprint.

1.2 MC68328 ARCHITECTURE

To improve total system throughput and reduce component count, board size, and cost of
system implementation, the MC68328 processor integrates a powerful MC68EC000 proces-
sor, intelligent peripheral modules, and typical system interface logic. These functions
include the system integration module (SIM28), timers, LCD controller, and more.

1.2.1 EC000 STATIC CORE

The EC000 core is a core implementation of the M68000 32-bit microprocessor architecture.
The features of the EC000 core processor include:
• Low power, static HCMOS implementation
• 32-bit address bus, 16-bit data bus
• Seventeen 32-bit data and address registers
• 56 powerful instruction types that support high-level development languages
• 14 addressing modes and 5 main data types
• 7 priority levels for interrupt control
The EC000 core is completely upward user code-compatible with all other members of the
M68000 microprocessor families and thus has access to a broad base of established real-
time kernels, operating systems, languages, applications, and development tools.
1.2.1.1 EC000 CORE PROGRAMMING MODEL. The EC000 core offers sixteen 32-bit
registers and a 32-bit program counter (see Figure 1-1). The first 8 registers (D7–D0) serve
as data registers for byte (8-bit), word (16-bit) and long-word (32-bit) operations. Because
using data registers will affect the condition-code register (which indicates negative number,
carry, and overflow conditions), they (the data registers) are used primarily for data manip-
ulation. The second set of 7 registers (A6–A0) and the user stack pointer (USP) may func-
tion as software stack pointers and base-address registers. These registers can be used for
word and long-word operations and do not affect the condition-code register. All of the reg-
isters (D7–D0 and A6–A0) may serve as index registers.
In supervisor mode, the upper byte of the status register (SR) and the supervisor stack
pointer (SSP) are also available to programmers. These registers are shown in Figure 1-3.
The SR (refer to Figure 1-3) contains the interrupt mask (7 levels available) as well as these
condition codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional
status bits indicate whether the processor is in trace mode (T-bit) or in supervisor/ user state
(S-bit).
1.2.1.2 DATA TYPES AND ADDRESS MODES. Five basic data types are supported:
1. Bits
2. Binary-coded decimal (BCD) digits (4 bits)
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