ST STM32G4 Series Reference Manual page 1523

RM0440
Bit 6 FMT: Hour format
Bit 5 BYPSHAD: Bypass the shadow registers
Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,
Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Timestamp event active edge
Bits 2:0 WUCKSEL[2:0]: ck_wut wakeup clock selection
Note: Bits 6 and 4 of this register can be written in initialization mode only (RTC_ICSR/INITF = 1).
WUT = wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
34.6.8 RTC write protection register (RTC_WPR)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
0: 24 hour/day format
1: AM/PM hour format
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
BYPSHAD must be set to 1.
0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
0: RTC_TS input rising edge generates a timestamp event
1: RTC_TS input falling edge generates a timestamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 2
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res.
w w
RM0440 Rev 1
Real-time clock (RTC)
16
is added to the WUT counter value
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
KEY[7:0]
w w w w
17 16
Res. Res.
1 0
w w
1523/2083
1551