Figure 15.8 Detailed Description Of One Bit; Table 15.2 Limits For Settable Value - Renesas H8S Series Hardware Manual

Section 15 Controller Area Network (HCAN)
Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the
settable time quantum (tq).
SYNC_SEG
1 time quantum
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample
point, and SJW) are shown in table 15.2.

Table 15.2 Limits for Settable Value

Name
Time segment 1
Time segment 2
Baud rate prescaler
Bit sample point
Re-synchronization jump width
Notes: 1. SJW is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
Rev. 6.00 Mar 15, 2006 page 418 of 570
REJ09B0211-0600
1-bit time (8 to 25 time quanta)
PRSEG
Time segment 1 (TSEG1)
2 to 16 time quanta

Figure 15.8 Detailed Description of One Bit

Abbreviation
TSEG1
TSEG2
BRP
BSP
SJW *
PHSEG1
Time segment 2
Min Value
B'0011 *
2
B'001 *
3
B'000000
B'0
1
B'00
PHSEG2
(TSEG2)
Max Value
B'1111
B'111
B'111111
B'1
B'11