Transmit Wait Register (Txpr) - Renesas H8S Series Hardware Manual

Section 15 Controller Area Network (HCAN)
15.3.5

Transmit Wait Register (TXPR)

The transmit wait register (TXPR) is a 16-bit register that is used to set a transmit wait after a
transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).
Bit Bit Name
15 TXPR7
14 TXPR6
13 TXPR5
12 TXPR4
11 TXPR3
10 TXPR2
9 TXPR1
8 —
7 TXPR15
6 TXPR14
5 TXPR13
4 TXPR12
3 TXPR11
2
TXPR10
1 TXPR9
0 TXPR8
Rev. 6.00 Mar 15, 2006 page 394 of 570
REJ09B0211-0600
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
These bits set a transmit wait (CAN bus arbitration
wait) for the corresponding mailboxes 1 to 15.
When TXPRn (n = 1 to 15) is set to 1, the message
in mailbox n becomes the transmit wait state.
[Clearing conditions]
•
Completion of message transmission
•
Completion of transmission cancellation
Bit 8 is reserved. This bit is always read as 1 and
the write value should always be 1.