Appendix; I/O Port States In Each Pin State - Renesas H8S/2100 Series Hardware Manual

A.

I/O Port States in Each Pin State

Table A.1 I/O Port States in Each Pin State
Port Name
Pin Name Reset
Port 1 T
Port 2 T
Port 3 T
Port 4 T
Ports 52 to 50 T
Port 6 T
Ports 7 and E4 to T
E1
Port 8 T
Port 97 T
Port 96 T
φ,
EXCL
Ports 95 to 90 T
Ports A to D, T
F, G, and H5 to H0
Port E0 T
Port I T
Port J T
[Legend]
H: High level
L: Low level
T: High impedance
keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up
MOS remains on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR.
DDR: Data direction register

Appendix

Software
Standby Mode Watch Mode
keep keep
keep keep
keep keep
keep keep
keep keep
keep keep
T T
keep keep
keep keep
[DDR = 1]H EXCL input/
keep
[DDR = 0]T
keep keep
keep keep
T ExEXCL input/T
keep keep
keep keep
Sleep Mode
keep
keep
keep
keep
keep
keep
T
keep
keep
[DDR = 1]
Clock output
[DDR = 0]T
keep
keep
T
keep
keep
Rev. 1.00 Apr. 28, 2008 Page 983 of 994
REJ09B0452-0100
Appendix
Program
Execution State
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Input port
I/O port
I/O port
Clock output/
EXCL input/
Input port
I/O port
I/O port
ExEXCL input/
input port
I/O port
I/O port