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I
FUNCTIONAL DESCRIPTION
available bus bandwidth. RONR may be used when it is important for
all of the MVME135/136 modules to have fair access to VMEbus.
Other bus masters that are not equipped with the RONR feature may
starve the VME135 from access to the VMEbus, since the MVME135/136
is attempt i ng to be fa i r and the other bus masters are not.
It
may be necessary to experiment with different configurations of
VMEbus arbitration levels and implementations of RONR operation
with other VMEbus masters. Also, experimentation with the system
configuration
with
respect
to
position
within
the
VMEbus
arbi trat ion da i sy-cha i n is recommended.
H&H
< Halt and Hol d Bi t>
This bit enables another VMEbus master to place the module in halt
by setting this bit. This ability is provided to allow upload and
download of the DRAM with the local processor operation suspended.
SIGLP
<
Signal low Priority>
The local processor may be interrupted by asserting this bit
location.
There is a control bit in the local control registers
that will allow this interrupt to occur (SLPIEN in < eNT3». This
is a level 2 interrupt to the local processor.
SIGHP
< Signal High Priority>
The local processor may be interrupted by asserting this bit
location. There is a control bit in the local CSR that will allow
this interrupt to occur (SHPIEN in < CNT3».
This signal is a
higher priority locally (level 5) than SIGLP.
MP0-MP3
< Mul t i-Processor Bi ts>
These are read/write bits in the most significant bit of each byte
they occupy. They may be used as semaphores or as handshake bits
for passing information through the MP COMMunication (MP COMM)
channel described below.
MP COMM
< Multi-Processor Communication Byte>
This is a byte wide communications path that allows interaction to
be accompl i shed between bus masters independently of DRAM.
4.16.1 Base Address Selection
The MVME135/136 modules have an a-position switch (S3) for locating
the MPCSRs, as well as the local DRAM, in the VMEbus address space. A
total of eight groups is accommodated and within each group a unique
base address for up to 31 processor modules can be selected. The
32nd address range for each group is reserved for location monitor
accesses capable of broadcasting an interrupt to all processor
4-32
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