Timing Issues; Clock Synchronization (Srts And Adaptive Fifos); Mapping Tdm Time Slots To Vcs; Cas Support - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
cope with the ATM networkÕs CDV), set ATM RxBD[I]. When the receive buffer is full, the
RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit polarity), and the
core is interrupted. The core then starts the MCC transmitter.

29.9.3 Timing Issues

Use of the TDM interface assumes that all communicating entities are synchronized (that
is, that they are using a synchronized serial clock). If the TDM interfaces are not
synchronized, a slip can occur in the reassembly buffer. If a buffer-not-ready event occurs
at the MCC transmitter, the user must restart the MCC transmit channel. If a buffer-not-
ready event occurs at the ATM transmitter, the user must restart the ATM transmit channel.

29.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)

Clock synchronization methods, such as using a time stamp (SRTS) or adaptive FIFOs,
prevent buffer slipping during reassembly. The SRTS method may be implemented using
external logic. The MPC8260 can read the SRTS from external logic and insert it into
AAL1 cells, and can track the SRTS from AAL1 cells and deliver it to external logic. See
Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó
Alternatively, an adaptive FIFOs method can be implemented using the core to maintain the
bridging buffer at a mid-level point. The difference between the MCC and ATM data
pointers is a measure of buffer synchronization. The core calculates the difference between
pointers at regular intervals and adapts the TDM clock accordingly to hold the difference
constant.

29.9.5 Mapping TDM Time Slots to VCs

Using the MCC and the SI, any TDM time-slot combination can be routed to a speciÞc data
buffer. (See Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó and Chapter 14, ÒSerial
Interface with Time-Slot Assigner.Ó) The same data buffers should be used by the ATM
controller to route receive and transmit data. For information about ATM buffers see
Section 29.10.5, ÒATM Controller Buffer Descriptors (BDs).Ó

29.9.6 CAS Support

For applications requiring channel-associated signaling (CAS), circuit emulation with CAS
requires additional core processing. External framers perform the CAS manipulation
through a serial or parallel interface.
When the MCC receives a multi-frame block, it generates an interrupt to the core. The core
reads the CAS block from the external framer and places it at the end of the ATM data buffer
after the structured multi-frame block. The core then passes the buffer pointer to the ATM
controller, and the controller packs the data and CAS block into AAL1 cells. All AAL1
functions, such as generating PDU-headers and structured pointers, operate normally.
When the ATM controller receives a multi-frame block, it generates an interrupt to the core.
The core reads the CAS block from the data buffer and writes it to the external framer. The
29-36 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA