Processor Bus Request Timing - Motorola M68060 User Manual

BUS AM-EX
ARBITRATION
STATE
C1
BCLK
A31–A0
TRANSFER
ATTRIBUTES
TS
TA
D31–D0
BR
BG
BB
BTT
AM_BR*
AM_BG*
* AM indicates the alternate bus master.
Figure 7-44 illustrates a functional timing diagram for an arbitration of a relinquish and retry
operation (MC68040 acknowledge termination mode). In Figure 7-44, the processor read
access that begins in C1 is terminated at the end of C2 with a retry request and BG negated,
forcing the processor to relinquish the bus and allow the alternate master to access the bus.
Note that the processor re-asserts BR during C3 since the original access is pending again.
After alternate bus master ownership, the bus is granted to the processor to allow it to retry
the access beginning in C7.
Figure 7-45 is a functional timing diagram for implicit ownership of the bus.
Figure 7-46 illustrates the effect of BGR on bus arbitration activity during locked sequences.
When BGR is asserted while BG is negated, locked sequences can be broken. Otherwise,
the entire locked sequence of bus cycles are completed by the processor before relinquish-
ing the bus.
MOTOROLA
AM-EX AM-EX EX-OWN
C2 C3 C4
ALTERNATE
MASTER
Figure 7-43. Processor Bus Request Timing
M68060 USER'S MANUAL
EX-OWN EX-OWN EX-OWN
C5 C6 C7
PROCESSOR
Bus Operation
END-TEN AM-IMP AM-EX
C10
C8 C9
ALTERNATE
MASTER
7-67