Transfer Burst (Tbst); Transfer Burst (Tbst)-Output; Transfer Burst (Tbst)-Input; Cache Inhibit (Ci)-Output - Motorola MPC750 User Manual

Table 7-3. Data Transfer Size (Continued)
TBST TSIZ[D-2] Transfer Size
Negated 100 4 bytes
Negated 101
5 bytes 1
Negated 110
6 bytes 1
Negated
111
7 bytes 1
Note: 1Not generated by MPC750.
7.2.4.3 Transfer Burst (TBST)
The transfer burst (TBST) signal is an input/output signal on the MPC750.
7.2.4.3.1 Transfer Burst {TBST)-Output
Following are the state meaning and timing comments for the TBST output signal.
State Meaning Asserted-Indicates that a burst transfer is in progress.
Negated-Indicates that a burst transfer is not in progress.
For external control instructions (eciwx and ecowx), TBST is used to
output bit 28 of the EAR, which is used to form the resource ID
(TBSTIITSIZO-TSIZ2).
Timing Comments AssertionlNegation-The same asA[O-31].
High Impedance-The same as A[0-31].
7.2.4.3.2 Transfer Burst {TBST)-Input
Following are the state meaning and timing comments for the TBST input signal.
State Meaning AssertedlNegated-Used when snooping for single-beat reads (read
with no intent to cache).
Timing Comments AssertionlNegation-The same asA[O-31].
7.2.4.4 Cache Inhibit (CI)-Output
The cache inhibit (CI) signal is an output signal on the MPC750. Following are the state
meaning and timing comments for the CI signal.
State Meaning Asserted-Indicates that a single-beat transfer will not be cached,
reflecting the setting of the I bit for the block or page that contains
the address of the current transaction.
Negated-Indicates that a burst transfer will allocate an MPC750
data cache block.
Timing Comments AssertionlNegation-The same asA[0-31].
High Impedance-The same as A[0-31].
7-12 MPC750 RISC Microprocessor User's Manual