Data Alu Input Registers (X0, Y1, And Y0); Data Alu Accumulator Registers; Figure 3-2 Data Alu Programming Model - Motorola DSP56800 Manual

Data Arithmetic Logic Unit
15
3.1.1

Data ALU Input Registers (X0, Y1, and Y0)

The data ALU registers (X0, Y1, and Y0) are 16-bit registers that serve as inputs for the data ALU. Each
register may be read or written by the CGDB as a word operand. They may be treated as three independent
16-bit registers, or as one 16-bit register and one 32-bit register. Y1 and Y0 can be concatenated to form
the 32-bit register Y, with Y1 being the most significant word and Y0 being the least significant word.
Figure 3-2 shows this arrangement.
These data ALU input registers are used as source operands for most data ALU operations and allow new
operands to be loaded from the memory for the next instruction while the register contents are used by the
current instruction. X0 may also be written by the XDB2 during the dual read instruction. Certain
arithmetic operations also allow these registers to be specified as destinations.
3.1.2

Data ALU Accumulator Registers

The two 36-bit data ALU accumulator registers can be accessed either as a 36-bit register (A or B) or as the
following, individual portions of the register:
• 4-bit extension register (A2 or B2)
• 16-bit MSP (A1 or B1)
• 16-bit LSP (A0 or B0)
The three individual portions make up the entire accumulator register, as shown in Figure 3-2.
These two techniques for accessing the accumulator registers provide important flexibility for both DSP
algorithms and general-purpose computing tasks. Accessing these registers as entire accumulators (A or B)
is particularly useful for DSP tasks, because this preserves the full precision of multiplication and other
ALU operations. Data limiting and saturation are also possible using the full registers, in cases where the
final result of a computation that has overflowed is moved (see Section 3.4.1, "Data Limiter," on page
3-26).
3-4
Data Arithmetic Logic Unit
Data ALU Input Registers
0
X0 Y
15
Accumulator Registers
35 32 31
A A2 A1
3 0 15
35 32 31
B B2 B1
3 0 15
Figure 3-2. Data ALU Programming Model
DSP56800 Family Manual
31 16 15
Y1
0 15
16 15
A0
0 15
16 15
B0
0 15
0
Y0
0
0
0
0
AA0035
0