ST STM32L4+ Series Reference Manual page 1583

RM0432
46.6.16 RTC tamper configuration register (RTC_TAMPCR)
Address offset: 0x40
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
TAMP TAMPPRCH
TAMPFLT[1:0]
PUDIS [1:0]
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TAMP3MF: Tamper 3 mask flag
0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to
allow next tamper event detection.
1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by
hardware. The backup registers are not erased.
Note: The Tamper 3 interrupt must not be enabled when TAMP3MF is set.
Bit 23 TAMP3NOERASE: Tamper 3 no erase
0: Tamper 3 event erases the backup registers.
1: Tamper 3 event does not erase the backup registers.
Bit 22 TAMP3IE: Tamper 3 interrupt enable
0: Tamper 3 interrupt is disabled if TAMPIE = 0.
1: Tamper 3 interrupt enabled.
Bit 21 TAMP2MF: Tamper 2 mask flag
0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to
allow next tamper event detection.
1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by
hardware. The backup registers are not erased.
Note: The Tamper 2 interrupt must not be enabled when TAMP2MF is set.
Bit 20 TAMP2NOERASE: Tamper 2 no erase
0: Tamper 2 event erases the backup registers.
1: Tamper 2 event does not erase the backup registers.
Bit 19 TAMP2IE: Tamper 2 interrupt enable
0: Tamper 2 interrupt is disabled if TAMPIE = 0.
1: Tamper 2 interrupt enabled.
Bit 18 TAMP1MF: Tamper 1 mask flag
0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to
allow next tamper event detection.
1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by
hardware.The backup registers are not erased.
Note: The Tamper 1 interrupt must not be enabled when TAMP1MF is set.
Real-time clock (RTC) applied to STM32L4Rxxx and STM32L4Sxxx only
28 27 26 25
Res. Res. Res.
12 11 10 9
TAMPFREQ[2:0]
rw rw rw rw
24 23 22
TAMP3
TAMP3 TAMP3 TAMP2
NO
MF IE
ERASE
rw rw rw
8 7 6
TAMP TAMP3 TAMP3
TS TRG
rw rw rw
RM0432 Rev 6
21 20 19 18
TAMP2
TAMP2 TAMP1
NO
MF IE MF
ERASE
rw rw rw rw
5 4 3 2
TAMP2 TAMP2 TAMPI
E TRG E E
rw rw rw rw
17 16
TAMP1
TAMP1
NO
IE
ERASE
rw rw
1 0
TAMP1 TAMP1
TRG E
rw rw
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