Exit From Software Standby Mode; Selection Of Waiting Time For Exit From Software Standby Mode - Renesas F-ZTAT H8 Series Hardware Manual

Section 21 Power-Down State
When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before
setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
21.4.2

Exit from Software Standby Mode

Software standby mode can be exited by input of an external interrupt at the NMI, IRQ
IRQ pin, or by input at the RES or STBY pin.
2
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ
0
CPU.
Exit by RES RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
RES RES
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY STBY Input: Low input at the STBY pin causes a transition to hardware standby mode. STBY STBY
21.4.3

Selection of Waiting Time for Exit from Software Standby Mode

Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 21.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies. Refer to table 21.3 for the
operating frequency and the waiting time needed for the oscillator to settle.
External Clock: Any values may be set.
Rev. 7.00 Sep 21, 2005 page 670 of 878
REJ09B0259-0700
, IRQ
0
, IRQ , and IRQ are cleared to 0, or if these interrupts are masked in the
1 2
, or IRQ interrupt request signal is received, the
1 2
, IRQ
, or
0 1