Dual Dac Channel Conversion - ST STM32L4x6 Reference Manual

RM0351
The steps to perform a user trimming calibration are as below:
1. If the DAC channel is active, Write 0 to ENx bit in DAC_CR to disable the channel.
2. Select a mode where the buffer is enabled, by writing to DACx_MCR register,
MODEx[2:0] = 000b or 001b or 100b or 101b,
3. Write DACx_DHR12Rx[11:0] with the middle code: 0x800 value,
4. Start the DAC channelx calibration, by setting the CENx bit in DACx_CR register to 1,
5. Apply a trimming algorithm:
a)
b)
c)
d)
The software algorithm may use either a successive approximation or dichotomy techniques
to compute and set the content of OTRIMx[4:0] bits in a faster way,
The commutation/toggle of CAL_FLAGx bit indicates that the offset is correctly
compensated and the corresponding trim code must be kept in the OTRIMx[4:0] bits in
DAC_CCR register.
Note: 1 A tOFFTRIMmax delay must be respected between the write to the OTRIMx[4:0] bits and
the read of the CAL_FLAGx bit in DAC_SR register in order to get a correct value.This
parameter is specified into datasheet electrical characteristics section.
2 If the VDD/VDDA, VREF+ and temperature conditions will not change during the MCU
operation while it enters more often in standby and VBAT mode, the software may store the
OTRIMx[4:0] bits found in the first user calibration in the flash or in back-up registers. then to
load/write them directly when the MCU power is back again thus avoiding to wait for a new
calibration time.
17.3.12

Dual DAC channel conversion

To efficiently use the bus bandwidth in applications that require the two DAC channels at the
same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A
unique register access is then required to drive both DAC channels at the same time.
Eleven possible conversion modes are possible using the two DAC channels and these dual
registers. All the conversion modes can nevertheless be obtained using separate DHRx
registers if needed.
All modes are described in the paragraphs below.
Independent trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
• Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
Write a code into OTRIMx[4:0] bits, starting by 00000b
Wait for tOFFTRIMmax delay
Check if CAL_FLAGx bit in DACx_SR is set to 1
if CAL_FLAGx is set to 1 the trimming code OTRIMx[4:0] is found and will be used
during operation to compensate the output value, else increment OTRIMx[4:0] and
repeat sub-steps from (a) to (d) again.
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Digital-to-analog converter (DAC)
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