Flash Control Register (Flash_Cr) - ST STM32L4x6 Reference Manual

Embedded Flash memory (FLASH)
3.7.6

Flash control register (FLASH_CR)

Address offset: 0x14
Reset value: 0xC000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29 28
OPT
LOCK Res. Res.
LOCK
rs rs
15 14 13 12
MER2 Res. Res. Res.
rw
Bits 29:28 Reserved, must be kept at reset value.
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Bit 3 PROGERR: Programming error
Set by hardware when a double-word address to be programmed contains a
value different from '0xFFFF FFFF' before programming, except if the data to
write is '0x0000 0000'.
Cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error
Set by hardware when a Flash memory operation (program / erase) completes
unsuccessfully.
This bit is set only if error interrupts are enabled (ERRIE = 1).
Cleared by writing '1'.
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operation (programming /
erase) has been completed successfully.
This bit is set only if the end of operation interrupts are enabled (EOPIE = 1).
Cleared by writing 1.
27 26 25
OBL_ RD ERR
LAUNCH ERRIE IE
rc_w1 rw rw
11 10 9
BKER
rw rw rw
Bit 31 LOCK: FLASH_CR Lock
This bit is set only. When set, the FLASH_CR register is locked. It is cleared by
hardware after detecting the unlock sequence.
In case of an unsuccessful unlock operation, this bit remains set until the next
system reset.
Bit 30 OPTLOCK: Options Lock
This bit is set only. When set, all bits concerning user option in FLASH_CR
register and so option page are locked. This bit is cleared by hardware after
detecting the unlock sequence. The LOCK bit must be cleared before doing the
unlock sequence for OPTLOCK bit.
In case of an unsuccessful unlock operation, this bit remains set until the next
reset.
DocID024597 Rev 3
24 23 22 21
EOP
Res. Res. Res.
IE
rw
8 7 6 5
PNB[7:0]
rw rw rw rw
20 19 18 17
OPT
Res. Res. FSTPG
STRT
rw rs
4 3 2 1
MER1 PER
rw rw rw rw
RM0351
16
STRT
rs
0
PG
rw