Clock Interrupt Flag Register (Rcc_Cifr) - ST STM32L4x6 Reference Manual

RM0351
6.4.8

Clock interrupt flag register (RCC_CIFR)

Address offset: 0x1C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSF: LSE Clock security system interrupt flag
Bit 8 CSSF: Clock security system interrupt flag
Bit 7 PLLSAI2RDYF: PLLSAI2 ready interrupt flag
Bit 6 PLLSAI1RDYF: PLLSAI1 ready interrupt flag
Bit 5 PLLRDYF: PLL ready interrupt flag
Bit 4 HSERDYF: HSE ready interrupt flag
28 27 26 25
Res. Res. Res.
12 11 10 9
LSE
Res. Res.
CSSF
r
Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software setting the LSECSSC bit.
0: No clock security interrupt caused by LSE clock failure
1: Clock security interrupt caused by LSE clock failure
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Set by hardware when the PLLSAI2 locks and PLLSAI2RDYDIE is set.
Cleared by software setting the PLLSAI2RDYC bit.
0: No clock ready interrupt caused by PLLSAI2 lock
1: Clock ready interrupt caused by PLLSAI2 lock
Set by hardware when the PLLSAI1 locks and PLLSAI1RDYDIE is set.
Cleared by software setting the PLLSAI1RDYC bit.
0: No clock ready interrupt caused by PLLSAI1 lock
1: Clock ready interrupt caused by PLLSAI1 lock
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
PLLSAI PLLSAI PLL
CSSF
2RDYF 1RDYF RDYF
r r r r
Reset and clock control (RCC)
20 19 18
Res. Res. Res. Res.
4 3 2
HSE HSI MSI LSE
RDYF RDYF RDYF RDYF
r r r
17 16
Res.
1 0
LSI
RDYF
r r
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