Figure 317. Output Compare Mode, Toggle On Oc1; Pwm Mode - ST STM32L4x6 Reference Manual

RM0351
Procedure
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
–
–
–
–
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE='0', else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 316.
28.4.10

PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
Write OCxPE = 0 to disable preload register
Write CCxP = 0 to select active high polarity
Write CCxE = 1 to enable the output

Figure 317. Output compare mode, toggle on OC1

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General-purpose timers (TIM15/16/17)
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