Slave Ahb Interface - ST STM32L4x6 Reference Manual

Analog-to-digital converters (ADC)
16.3.5

Slave AHB interface

The ADCs implement an AHB slave port for control/status register and data access. The
features of the AHB interface are listed below:
•
Word (32-bit) accesses
•
Single cycle response
•
Response to all read/write accesses to the registers with zero wait states.
The AHB slave interface does not support split/retry requests, and never generates AHB
errors.
16.3.6 ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator
(ADVREGEN)
By default, the ADC is in deep-power-down mode where its supply is internally switched off
to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADCx_CR
register).
To start ADC operations, it is first needed to exit deep-power-down mode by setting bit
DEEPPWD=0.
Then, it is mandatory to enable the ADC internal voltage regulator by setting the bit
ADVREGEN=1 into ADCx_CR register. The software must wait for the startup time of the
ADC voltage regulator (T
ADC. This delay must be implemented by software.
For the startup time of the ADC voltage regulator, please refer to device datasheet for
T
ADCVREG_STUP
After ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to
save power by also disabling the ADC voltage regulator. This is done by writing bit
ADVREGEN=0.
Then, to save more power by reducing the leakage currents, it is also possible to re-enter in
ADC deep-power-down mode by setting bit DEEPPWD=1 into ADCx_CR register. This is
particularly interesting before entering STOP mode.
Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN
is automatically cleared.
Note: When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog
calibration is kept.
In ADC deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and it
is necessary to either relaunch a calibration or re-apply the calibration factor which was
previously saved (refer to
ADCx_CALFACT)).
16.3.7 Single-ended and differential input channels
Channels can be configured to be either single-ended input or differential input by writing
into bits DIFSEL[15:1] in the ADCx_DIFSEL register. This configuration must be written
while the ADC is disabled (ADEN=0). Note that DIFSEL[18:16] are fixed to single ended
channels (internal channels only) and are always read as 0.
In single-ended input mode, the analog voltage to be converted for channel "i" is the
difference between the external voltage ADC_INi (positive input) and V
436/1693
ADCVREG_STUP
parameter.
Section 16.3.8: Calibration (ADCAL, ADCALDIF,
DocID024597 Rev 3
) before launching a calibration or enabling the
RM0351
(negative input).
REF-