Syscfg Configuration Register 1 (Syscfg_Cfgr1) - ST STM32L4x6 Reference Manual

System configuration controller (SYSCFG)
Bit 8 FB_MODE: Flash Bank mode selection
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 MEM_MODE: Memory mapping selection
Note:
When the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1
memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap
mode, the CPU can access the external memory via ICode bus instead of System bus
which boosts up the performance.
8.2.2

SYSCFG configuration register 1 (SYSCFG_CFGR1)

Address offset: 0x04
Reset value: 0x7C00 0001
31 30 29
FPU_IE[5..0]
rw rw rw
15 14 13
Res Res Res
274/1693
0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 2
mapped at 0x0808 0000 (and aliased at 0x0008 0000)
1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 1
mapped at 0x0808 0000 (and aliased at 0x0008 0000)
These bits control the memory internal mapping at address 0x0000 0000. These bits are
used to select the physical remap by software and so, bypass the BOOT pin and the option
bit setting. After reset these bits take the value selected by BOOT0 pin and BOOT1 option
bit.
000: Main Flash memory mapped at 0x00000000.
001: System Flash memory mapped at 0x00000000.
010: FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
011: SRAM1 mapped at 0x00000000.
100: Reserved
101: Reserved
110: QUADSPI memory mapped at 0x00000000.
111: Reserved
28 27 26 25
Res
rw rw rw
12 11 10 9
Res Res Res Res
24 23 22
I2C3_
Res Res
FMP
rw
8 7 6
BOOST
Res Res
EN
rw
DocID024597 Rev 3
21 20 19 18
I2C_ I2C_
I2C2_ I2C1_
PB9_ PB8_
FMP FMP
FMP FMP
rw rw rw rw
5 4 3 2
Res Res Res Res
RM0351
17 16
I2C_ I2C_
PB7_ PB6_
FMP FMP
rw rw
1 0
Res FWDIS
rc_w0