Low-Power Modes - ST STM32L4x6 Reference Manual

RM0351
can be enabled to confirm whether the supply is present or not.
The following sequence must be done before using the USB_OTG peripheral:
1. If V
DDUSB
a)
b)
c)
d)
2. Set the USV bit in the
power isolation.
The following sequence must be done before using any I/O from PG[15:2]:
1. If V
DDIO2
a)
b)
c)
d)
2. Set the IOSV bit in the
power isolation.
The following sequence must be done before using any of these analog peripherals: analog
to digital converters, digital to analog converters, comparators, operational amplifiers,
voltage reference buffer:
1. If V
DDA
a)
b)
c)
d)
2. Enable the analog peripheral, which automatically removes the V
5.3

Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low-
power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.
The device features seven low-power modes:
•
Sleep mode: CPU clock off, all peripherals including Cortex
as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event
occurs. Refer to
• Low-power run mode: This mode is achieved when the system clock frequency is
reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The
is independent from V
Enable the PVM1 by setting PVME1 bit in the
(PWR_CR2).
Wait for the PVM1 wakeup time
Wait until PVMO1 bit is cleared in the
Optional: Disable the PVM1 for consumption saving.
Power control register 2 (PWR_CR2)
is independent from V
Enable the PVM2 by setting PVME2 bit in the
(PWR_CR2).
Wait for the PVM2 wakeup time
Wait until PVMO2 bit is cleared in the
Optional: Disable the PVM2 for consumption saving.
Power control register 2 (PWR_CR2)
is independent from V
Enable the PVM3 (or PVM4) by setting PVME3 (or PVME4) bit in the
control register 2 (PWR_CR2).
Wait for the PVM3 (or PVM4) wakeup time
Wait until PVMO3 (or PVMO4) bit is cleared in the
(PWR_SR2).
Optional: Disable the PVM3 (or PVM4) for consumption saving.
Section 5.3.4: Sleep
DocID024597 Rev 3
:
DD
Power control register 2
Power status register 2
:
DD
Power control register 2
Power status register 2
:
DD
mode.
Power control (PWR)
(PWR_SR2).
to remove the V
DDUSB
(PWR_SR2).
to remove the V
DDIO2
Power
Power status register 2
isolation.
DDA
®
-M4 core peripherals such
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