ST STM32L4x6 Reference Manual page 608

Digital filter for sigma delta modulators (DFSDM)
Channel inputs selection
Serial inputs (data and clock signals) from DFSDM_DATINy and DFSDM_CKINy pins can
be redirected from the following channel. The serial input channel redirection is set by
CHINSEL bit in DFSDM_CHCFGyR1 register.
Channel redirection can be used to collect audio data from PDM (pulse density modulation)
stereo microphone type. PDM stereo microphone has one data and one clock signal. Data
signal provides information for both left and right audio channel (rising clock edge samples
for left channel and falling clock edge samples for right channel).
Configuration of serial channels for PDM microphone input:
•
PDM microphone signals (data, clock) will be connected to DFSDM input serial channel
y (DFSDM_DATINy, DFSDM_CKINy).
•
Channel y will be configured: CHINSEL = 0 (input from channel y).
•
Channel (y-1) will be configured: CHINSEL = 1 (also input from channel y).
•
Channel y: SITP[1:0] = 0 (rising edge to strobe data) => left audio channel on channel
y.
• Channel (y-1): SITP[1:0] = 1 (falling edge to strobe data) => right audio channel on
channel y-1.
•
Two DFSDM filters will be assigned to channel y and channel (y-1) (to filter left and
right channels from PDM microphone).
Output clock generation
A clock signal can be provided on DFSDM_CKOUT pin to drive external Σ∆ modulator clock
inputs. The frequency of this DFSDM_CKOUT signal is derived from DFSDM clock or from
audio clock (see CKOUTSRC bit in DFSDM_CHCFG0R1 register) divided by a predivider
(see CKOUTDIV bits in DFSDM_CHCFG0R1 register). If the output clock is stopped, then
DFSDM_CKOUT signal is set to low state (output clock can be stopped by CKOUTDIV=0 in
DFSDM_CHCFGyR1 register or by DFSDMEN=0 in DFSDMx_CHCFG0R1 register). The
output clock stopping is performed:
•
4 system clocks after DFSDMEN is cleared (if CKOUTSRC=0)
•
1 system clock and 3 audio clocks after DFSDMEN is cleared (if CKOUTSRC=1)
Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid
glitch on DFSDM_CKOUT pin. The output clock signal frequency must be in the range 0 -
20 MHz.
SPI data input format operation
In SPI format, the data stream is sent in serial format through data and clock signals. Data
signal is always provided from DFSDM_DATINy pin. A clock signal can be provided
externally from DFSDM_CKINy pin or internally from a signal derived from the
DFSDM_CKOUT signal source.
In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on
DFSDM_DATINy pin) is sampled on rising or falling clock edge (of DFSDM_CKINy pin)
according SITP[1:0] bits setting (in DFSDM_CHCFGyR1 register).
608/1693 DocID024597 Rev 3
RM0351