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Reset and clock control (RCC)
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 LPTIM2SMEN Low power timer 2 clocks enable during Sleep and Stop modes
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 SWPMI1SMEN: Single wire protocol clocks enable during Sleep and Stop modes
Bit 1 Reserved, must be kept at reset value.
Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
240/1693
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Set and cleared by software.
0: LPTIM2 clocks disabled by the clock gating
1: LPTIM2 clocks enabled by the clock gating
Set and cleared by software.
0: SWPMI1 clocks disabled by the clock gating
1: SWPMI1 clocks enabled by the clock gating
Set and cleared by software.
0: LPUART1 clocks disabled by the clock gating
1: LPUART1 clocks enabled by the clock gating
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
(1)
(1)
(1)
(1)
DocID024597 Rev 3
21
20
19
Res.
Res.
Res.
Res.
5
4
3
SWP
LPTIM
Res.
Res.
2SMEN
SMEN
rw
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
RM0351
18
17
16
Res.
Res.
2
1
0
LP
MI1
Res.
UART1
SMEN
rw
rw
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