Table 167. Lptim Register Map And Reset Values - ST STM32L4x6 Reference Manual

RM0351
30.7.11 LPTIM register map
The following table summarizes the LPTIM registers.
Offset Register
LPTIMx_ISR
0x00
Reset value
LPTIMx_ICR
0x04
Reset value
LPTIMx_IER
0x08
Reset value
LPTIMx_CFGR
0x0C
Reset value
LPTIMx_CR
0x10
Reset value
LPTIMx_CMP
0x14
Reset value
LPTIMx_ARR
0x18
Reset value
LPTIMx_CNT
0x1C
Reset value
LPTIMx_OR
0x20
Reset Value
Refer to

Table 167. LPTIM register map and reset values

0 0 0 0 0 0 0 0
Section 2.2.2 on page 67 for the register boundary addresses.
DocID024597 Rev 3
Low-power timer (LPTIM)
0 0 0 0 0 0 0 0
CMP[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
CNT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0
0 0
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