Table 90. Tsar Timings Depending On Resolution; Programmable Resolution (Res) - Fast Conversion Mode - ST STM32L4x6 Reference Manual

RM0351
16.3.22

Programmable resolution (RES) - fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control
bits RES[1:0].
format with respect to the resolution as well as to the data alignment.
Lower resolution allows faster conversion time for applications where high-data precision is
not required. It reduces the conversion time spent by the successive approximation steps
according to
RES
(bits)
12
10
8
6
16.3.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)
The ADC notifies the application for each end of regular conversion (EOC) event and each
injected conversion (JEOC) event.
The ADC sets the EOC flag as soon as a new regular conversion data is available in the
ADCx_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by
the software either by writing 1 to it or by reading ADCx_DR.
The ADC sets the JEOC flag as soon as a new injected conversion data is available in one
of the ADCx_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is
cleared by the software either by writing 1 to it or by reading the corresponding ADCx_JDRy
register.
The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for
regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt
can be generated if bit EOSMPIE is set.
16.3.24 End of conversion sequence (EOS, JEOS)
The ADC notifies the application for each end of regular sequence (EOS) and for each end
of injected sequence (JEOS) event.
The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is
available in the ADCx_DR register. An interrupt can be generated if bit EOSIE is set. EOS
flag is cleared by the software either by writing 1 to it.
The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is
complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the
software either by writing 1 to it.
Figure 88, Figure
Table 90.
Table 90. T
T
SAR
(ADC clock cycles)
12.5 ADC clock cycles 156.25 ns
10.5 ADC clock cycles 131.25 ns
8.5 ADC clock cycles
6.5 ADC clock cycles
DocID024597 Rev 3
89, Figure 90 and Figure 91
timings depending on resolution
SAR
T
CONV
T (ns) at
SAR
(with Sampling Time=
F =80 MHz
ADC
2.5 ADC clock cycles)
15 ADC clock cycles
13 ADC clock cycles
106.25 ns 11 ADC clock cycles
81.25 ns 9 ADC clock cycles
Analog-to-digital converters (ADC)
show the conversion result
(ADC clock cycles)
187.5 ns
162.5 ns
137.5 ns
112.5 ns
T (ns) at
CONV
F =80 MHz
ADC
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