Interrupt Mask Register 1 (Exti_Imr1) - ST STM32L4x6 Reference Manual

RM0351
12.5 registers
EXTI
Refer to
The peripheral registers have to be accessed by words (32-bit).
12.5.1

Interrupt mask register 1 (EXTI_IMR1)

Address offset: 0x00
Reset value: 0xFF82 0000
31 30 29
IM31 IM30 IM29 IM28
rw rw rw
15 14 13
IM15 IM14 IM13 IM12
rw rw rw
Bits 31:0 IMx: Interrupt Mask on line x (x = 31 to 0)
Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39) is set to '1' in order
to enable the interrupt by default.
12.5.2 Event mask register 1 (EXTI_EMR1)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
EM31 EM30 EM29 EM28
rw rw rw
15 14 13
EM15 EM14 EM13 EM12
rw rw rw
Bits 31:0 EMx: Event mask on line x (x = 31 to 0)
Section 1.1 on page 61
28 27 26 25
IM27 IM26 IM25
rw rw rw rw
12 11 10 9
IM11 IM10 IM9
rw rw rw rw
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
28 27 26 25
EM27 EM26 EM25
rw rw rw rw
12 11 10 9
EM11 EM10 EM9
rw rw rw rw
0: Event request from line x is masked
1: Event request from line x is not masked
Extended interrupts and events controller (EXTI)
for a list of abbreviations used in register descriptions.
24 23 22
IM24 IM23 IM22
rw rw rw
8 7 6
IM8 IM7 IM6
rw rw rw
24 23 22
EM24 EM23 EM22
rw rw rw
8 7 6
EM8 EM7 EM6
rw rw rw
DocID024597 Rev 3
21 20 19 18
IM21 IM20 IM19 IM18
rw rw rw rw
5 4 3 2
IM5 IM4 IM3 IM2
rw rw rw rw
21 20 19 18
EM21 EM20 EM19 EM18
rw rw rw rw
5 4 3 2
EM5 EM4 EM3 EM2
rw rw rw rw
17 16
IM17 IM16
rw rw
1 0
IM1 IM0
rw rw
17 16
EM17 EM16
rw rw
1 0
EM1 EM0
rw rw
329/1693
336