Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr) - ST STM32L4x6 Reference Manual

Reset and clock control (RCC)
6.4.21

APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x60
Reset value: 0x0000 0000
Access: word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29
Res. Res. Res. Res.
15 14 13
USART
TIM8 SPI1
Res. 1
EN
EN
rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DFSDMEN: DFSDM timer clock enable
Set and cleared by software.
0: DFSDM clock disabled
1: DFSDM clock enabled
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2EN: SAI2 clock enable
Set and cleared by software.
0: SAI2 clock disabled
1: SAI2 clock enabled
Bit 21 SAI1EN: SAI1 clock enable
Set and cleared by software.
0: SAI1 clock disabled
1: SAI1 clock enabled
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 timer clock enable
Set and cleared by software.
0: TIM17 timer clock disabled
1: TIM17 timer clock enabled
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: TIM16 timer clock disabled
1: TIM16 timer clock enabled
Bit 16 TIM15EN: TIM15 timer clock enable
Set and cleared by software.
0: TIM15 timer clock disabled
1: TIM15 timer clock enabled
Bit 15 Reserved, must be kept at reset value.
232/1693
28 27 26 25
Res. Res. Res.
12 11 10 9
SDMMC
TIM1
1 Res.
EN EN
EN
rw rw rw
DocID024597 Rev 3
24 23 22
DFSDM SAI2 SAI1
Res.
EN EN EN
rw rw
8 7 6
FW
Res. Res. Res.
EN
rs
21 20 19 18
TIM
Res. Res.
17EN
rw rw
5 4 3 2
Res. Res. Res.
RM0351
17 16
TIM16 TIM15
EN EN
rw rw
1 0
SYS
Res.
CFGEN
rw