Flash Main Memory Programming Sequences - ST STM32L4x6 Reference Manual

RM0351
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the MER1 bit or/and MER2 (depending on the bank) in the
(FLASH_CR). The both banks can be selected in the same operation.
4. Set the STRT bit in the FLACH_CR register.
5. Wait for the BSY bit to be cleared in the
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.
If the bank to erase or if one of the banks to erase contains a write-protected area (by WRP
or PCROP), WRPERR is set and the mass erase request is aborted (for both banks if both
are selected).
3.3.7

Flash main memory programming sequences

The Flash memory is programmed 72 bits at a time (64 bits + 8 bits ECC).
Programming in a previously programmed address is not allowed except if the data to write
is full zero, and any attempt will set PROGERR flag in the
(FLASH_SR).
It is only possible to program double word (2 x 32-bit data).
•
Any attempt to write byte or half-word will set SIZERR flag in the FLASH_SR register.
•
Any attempt to write a double word which is not aligned with a double word address will
set PGAERR flag in the FLASH_SR register.
Standard programming
The Flash memory programming sequence in standard mode is as follows:
1. Check that no Flash main memory operation is ongoing by checking the BSY bit in the
Flash status register
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the PG bit in the
4. Perform the data write operation at the desired memory address, inside main memory
block or OTP area. Only double word can be programmed.
–
–
5. Wait until the BSY bit is cleared in the FLASH_SR register.
6. Check that EOP flag is set in the FLASH_SR register (meaning that the programming
operation has succeed), and clear it by software.
7. Clear the PG bit in the FLASH_SR register if there no more programming request
anymore.
Note: When the flash interface has received a good sequence (a double word), programming is
automatically launched and BSY bit is set. The internal oscillator HSI16 (16 MHz) is enabled
(FLASH_SR).
Flash control register
Write a first word in an address aligned with double word
Write the second word
DocID024597 Rev 3
Embedded Flash memory (FLASH)
Flash status register (FLASH_SR).
Flash status register
(FLASH_CR).
Flash control register
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