ST STM32L4x6 Reference Manual page 239

RM0351
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
Bit 10 Reserved, must be kept at reset value.
Bit 9 LCDSMEN: LCD clocks enable during Sleep and Stop modes
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes
Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes
Bit 3 TIM5SMEN: TIM5 timer clocks enable during Sleep and Stop modes
Bit 2 TIM4SMEN: TIM4 timer clocks enable during Sleep and Stop modes
Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes
Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
6.4.26 APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2)
Address offset: 0x7C
Reset value: 0x0000 0025
Access: no wait state, word, half-word and byte access
Set and cleared by software. This bit is forced to '1' by hardware when the hardware WWDG
option is activated.
0: Window watchdog clocks disabled by the clock gating
1: Window watchdog clocks enabled by the clock gating
Set and cleared by software.
0: LCD clocks disabled by the clock gating
1: LCD clocks enabled by the clock gating
Set and cleared by software.
0: TIM7 clocks disabled by the clock gating
1: TIM7 clocks enabled by the clock gating
Set and cleared by software.
0: TIM6 clocks disabled by the clock gating
1: TIM6 clocks enabled by the clock gating
Set and cleared by software.
0: TIM5 clocks disabled by the clock gating
1: TIM5 clocks enabled by the clock gating
Set and cleared by software.
0: TIM4 clocks disabled by the clock gating
1: TIM4 clocks enabled by the clock gating
Set and cleared by software.
0: TIM3 clocks disabled by the clock gating
1: TIM3 clocks enabled by the clock gating
Set and cleared by software.
0: TIM2 clocks disabled by the clock gating
1: TIM2 clocks enabled by the clock gating
DocID024597 Rev 3
Reset and clock control (RCC)
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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during Sleep and Stop modes
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