Voltage Regulator - ST STM32L4x6 Reference Manual

RM0351
Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to
2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source
(e.g. to drive a LED).
When the backup domain is supplied by V
V is not present), the following functions are available:
DD
•
PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to
RTC functional
•
PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as
tamper pins
Backup domain access
After a system reset, the backup domain (RTC registers and backup registers) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
1. Enable the power interface clock by setting the PWREN bits in the
APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
2. Set the DBP bit in the
backup domain
3. Select the RTC clock source in the
4. Enable the RTC clock by setting the RTCEN [15] bit in the
register
VBAT battery charging
When VDD is present, It is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 kOhm resistor
depending on the VBRS bit value in the PWR_CR4 register.
The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is
automatically disabled in VBAT mode.
5.1.6

Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the backup domain. The main regulator output voltage (V
programmed by software to two different power ranges (Range 1 and Range 2) in order to
optimize the consumption depending on the system's maximum operating frequency (refer
to Section 6.2.8: Clock source frequency versus voltage scaling
access latency.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the V
regulator (LPR).
•
In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the V
•
In low-power run and low-power sleep modes, the main regulator is off and the low-
power regulator (LPR) supplies low power to the V
description)
Power control register 1 (PWR_CR1)
(RCC_BDCR).
supply is provided either by the main regulator (MR) or by the low-power
CORE
DocID024597 Rev 3
(analog switch connected to V
BAT
Backup domain control register
domain (core, memories and digital peripherals).
CORE
CORE
Power control (PWR)
because
BAT
Section 34.3:
Section 6.4.19:
to enable access to the
(RCC_BDCR).
Backup domain control
CORE
and to Section 3.3.3: Read
domain, preserving the
) can be
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