Table 156. Timx Internal Trigger Connection; Tim15 Dma/Interrupt Enable Register (Tim15_Dier) - ST STM32L4x6 Reference Manual

RM0351
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input Control register and Control Register
description.
0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal
clock.
0001: Reserved
0010: Reserved
0011: Reserved
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
reinitializes the counter, generates an update of the registers and starts the counter.
Other codes: reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
Note: The clock of the slave timer must be enabled prior to receive events from the master
Slave TIM
TIM15
28.5.4

TIM15 DMA/interrupt enable register (TIM15_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
COMD
Res. TDE Res.
E
rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
Bits 12:11 Reserved, must be kept at reset value.
(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
timer, and must not be changed on-the-fly while triggers are received from the master
timer.

Table 156. TIMx Internal trigger connection

ITR0 (TS = 000)
TIM1
12 11 10 9
Res. CC2DE CC1DE
rw rw
DocID024597 Rev 3
General-purpose timers (TIM15/16/17)
ITR1 (TS = 001)
TIM3
8 7 6 5
UDE BIE TIE COMIE
rw rw rw rw
ITR2 (TS = 010) ITR3 (TS = 011)
TIM16 OC1 TIM17 OC1
4 3 2
Res. Res. CC2IE
rw
1 0
CC1IE UIE
rw rw
969/1693
1009