ST STM32L4x6 Reference Manual page 454

Analog-to-digital converters (ADC)
All the parameters of the context are defined into a single register ADCx_JSQR and this
register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of
parameters:
•
The JSQR register can be written at any moment even when injected conversions are
ongoing.
•
Each data written into the JSQR register is stored into the Queue of context.
•
At the beginning, the Queue is empty and the first write access into the JSQR register
immediately changes the context and the ADC is ready to receive injected triggers.
•
Once an injected sequence is complete, the Queue is consumed and the context
changes according to the next JSQR parameters stored in the Queue. This new
context is applied for the next injected sequence of conversions.
•
A Queue overflow occurs when writing into register JSQR while the Queue is full. This
overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the
write access of JSQR register which has created the overflow is ignored and the queue
of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.
•
Two possible behaviors are possible when the Queue becomes empty, depending on
the value of the control bit JQM of register ADCx_CFGR:
–
–
•
Reading JSQR register returns the current JSQR context which is active at that
moment. When the JSQR context is empty, JSQR is read as 0x0000.
•
The Queue is flushed when stopping injected conversions by setting JADSTP=1 or
when disabling the ADC by setting ADDIS=1:
–
–
Note: When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the
injected sequence changes the context and consumes the Queue.The 1
consumes the queue but others are still valid triggers as shown by the discontinuous mode
example below (length = 3 for both contexts):
st
•
1 trigger, discontinuous. Sequence 1: context 1 consumed, 1
nd
•
2
rd
•
3 trigger, discontinuous. Sequence 1: 3
th
•
4 trigger, discontinuous. Sequence 2: context 2 consumed, 1
th
•
5 trigger, discontinuous. Sequence 2: 2
th
•
6 trigger, discontinuous. Sequence 2: 3
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If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be
empty during run operations: the Queue always maintains the last active context
and any further valid start of injected sequence will be served according to the last
active context.
If JQM=1, the Queue can be empty after the end of an injected sequence or if the
Queue is flushed. When this occurs, there is no more context in the queue and
hardware triggers are disabled. Therefore, any further hardware injected triggers
are ignored until the software re-writes a new injected context into JSQR register.
If JQM=0, the Queue is maintained with the last active context.
If JQM=1, the Queue becomes empty and triggers are ignored.
trigger, disc. Sequence 1: 2
nd
conversion.
rd
conversion.
nd
conversion.
rd
conversion.
DocID024597 Rev 3
RM0351
st
trigger only
st
conversion carried out
st
conversion carried out.