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STM32F102 series
ST STM32F102 series Manuals
Manuals and User Guides for ST STM32F102 series. We have
3
ST STM32F102 series manuals available for free PDF download: Reference Manual, Application Note
ST STM32F102 series Reference Manual (1128 pages)
advanced ARM-based 32-bit MCUs
Brand:
ST
| Category:
Controller
| Size: 11 MB
Table of Contents
Table of Contents
2
Overview of the Manual
40
Table 1. Sections Related to each Stm32F10Xxx Product
40
Table 2. Sections Related to each Peripheral
43
Documentation Conventions
47
List of Abbreviations for Registers
47
Glossary
47
Peripheral Availability
47
Memory and Bus Architecture
48
System Architecture
48
Figure 1. System Architecture (Low-, Medium-, XL-Density Devices)
48
Figure 2. System Architecture in Connectivity Line Devices
49
Memory Organization
50
Memory Map
51
Table 3. Register Boundary Addresses
51
Bit Banding
54
Embedded SRAM
54
Embedded Flash Memory
55
Table 4. Flash Module Organization (Low-Density Devices)
55
Table 5. Flash Module Organization (Medium-Density Devices)
56
Table 6. Flash Module Organization (High-Density Devices)
57
Table 7. Flash Module Organization (Connectivity Line Devices)
57
Table 8. XL-Density Flash Module Organization
58
Boot Configuration
61
Table 9. Boot Modes
61
CRC Calculation Unit
64
CRC Introduction
64
CRC Main Features
64
Figure 3. CRC Calculation Unit Block Diagram
64
CRC Functional Description
65
CRC Registers
65
Data Register (CRC_DR)
65
Independent Data Register (CRC_IDR)
65
Control Register (CRC_CR)
66
CRC Register Map
66
Table 10. CRC Calculation Unit Register Map and Reset Values
66
Power Control (PWR)
67
Power Supplies
67
Independent A/D and D/A Converter Supply and Reference Voltage
68
Figure 4. Power Supply Overview
68
Battery Backup Domain
69
Voltage Regulator
70
Power Supply Supervisor
70
Power on Reset (Por)/Power down Reset (PDR)
70
Programmable Voltage Detector (PVD)
70
Figure 5. Power on Reset/Power down Reset Waveform
70
Figure 6. PVD Thresholds
71
Low-Power Modes
72
Slowing down System Clocks
72
Table 11. Low-Power Mode Summary
72
Peripheral Clock Gating
73
Sleep Mode
73
Stop Mode
74
Table 12. Sleep-Now
74
Table 13. Sleep-On-Exit
74
Table 14. Stop Mode
75
Standby Mode
76
Table 15. Standby Mode
76
Auto-Wakeup (AWU) from Low-Power Mode
77
Power Control Registers
77
Power Control Register (PWR_CR)
77
Power Control/Status Register (PWR_CSR)
79
PWR Register Map
80
Table 16. PWR Register Map and Reset Values
80
Backup Registers (BKP)
81
BKP Introduction
81
BKP Main Features
81
BKP Functional Description
82
Tamper Detection
82
RTC Calibration
82
BKP Registers
83
Backup Data Register X (Bkp_Drx) (X = 1
83
RTC Clock Calibration Register (BKP_RTCCR)
83
Backup Control Register (BKP_CR)
84
Backup Control/Status Register (BKP_CSR)
84
BKP Register Map
85
Table 17. BKP Register Map and Reset Values
85
Low-, Medium-, High- and XL-Density Reset and Clock Control (RCC)
90
Reset
90
System Reset
90
Power Reset
91
Figure 7. Simplified Diagram of the Reset Circuit
91
Backup Domain Reset
92
Clocks
92
Figure 8. Clock Tree
93
Figure 9. HSE/ LSE Clock Sources
94
HSE Clock
94
HSI Clock
95
Pll
96
LSE Clock
96
LSI Clock
96
System Clock (SYSCLK) Selection
97
Clock Security System (CSS)
97
RTC Clock
98
Watchdog Clock
98
Clock-Out Capability
98
RCC Registers
99
Clock Control Register (RCC_CR)
99
Clock Configuration Register (RCC_CFGR)
101
Clock Interrupt Register (RCC_CIR)
104
APB2 Peripheral Reset Register (RCC_APB2RSTR)
106
APB1 Peripheral Reset Register (RCC_APB1RSTR)
109
AHB Peripheral Clock Enable Register (RCC_AHBENR)
111
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
112
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
115
Backup Domain Control Register (RCC_BDCR)
118
Control/Status Register (RCC_CSR)
119
RCC Register Map
121
Table 18. RCC Register Map and Reset Values
121
Connectivity Line Devices: Reset and Clock Control (RCC)
123
Reset
123
System Reset
123
Power Reset
124
Figure 10. Simplified Diagram of the Reset Circuit
124
Backup Domain Reset
125
Clocks
125
Figure 11. Clock Tree
126
HSE Clock
127
Figure 12. HSE/ LSE Clock Sources
128
HSI Clock
128
LSE Clock
129
Plls
129
LSI Clock
130
System Clock (SYSCLK) Selection
130
Clock Security System (CSS)
131
RTC Clock
131
Watchdog Clock
131
Clock-Out Capability
132
RCC Registers
132
Clock Control Register (RCC_CR)
132
Clock Configuration Register (RCC_CFGR)
134
Clock Interrupt Register (RCC_CIR)
137
APB2 Peripheral Reset Register (RCC_APB2RSTR)
141
APB1 Peripheral Reset Register (RCC_APB1RSTR)
142
AHB Peripheral Clock Enable Register (RCC_AHBENR)
145
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
146
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
148
Backup Domain Control Register (RCC_BDCR)
150
Control/Status Register (RCC_CSR)
152
AHB Peripheral Clock Reset Register (RCC_AHBRSTR)
153
Clock Configuration Register2 (RCC_CFGR2)
154
RCC Register Map
156
Table 19. RCC Register Map and Reset Values
156
General-Purpose and Alternate-Function I/Os (Gpios and Afios)
159
GPIO Functional Description
159
Figure 13. Basic Structure of a Standard I/O Port Bit
160
Figure 14. Basic Structure of a Five-Volt Tolerant I/O Port Bit
160
Atomic Bit Set or Reset
161
General-Purpose I/O (GPIO)
161
Table 20. Port Bit Configuration Table
161
Table 21. Output MODE Bits
161
Alternate Functions (AF)
162
External Interrupt/Wakeup Lines
162
GPIO Locking Mechanism
162
Software Remapping of I/O Alternate Functions
162
Figure 15. Input Floating/Pull Up/Pull down Configurations
163
Input Configuration
163
Figure 16. Output Configuration
164
Output Configuration
164
Alternate Function Configuration
165
Figure 17. Alternate Function Configuration
165
Analog Configuration
166
Figure 18. High Impedance-Analog Configuration
166
GPIO Configurations for Device Peripherals
166
Table 22. Advanced Timers TIM1/TIM8
166
Table 23. General-Purpose Timers TIM2/3/4/5
167
Table 24. Usarts
167
Table 25. SPI
167
Table 26. I2S
168
Table 27. I2C
168
Table 28. Bxcan
168
Table 29. USB
168
Table 30. OTG_FS Pin Configuration
168
Figure 19. ADC / DAC
169
Table 31. SDIO
169
Table 32. FSMC
169
Table 33. Other Ios
170
GPIO Registers
171
Port Configuration Register Low (Gpiox_Crl) (X=A..g
171
Port Configuration Register High (Gpiox_Crh) (X=A..g
172
Port Input Data Register (Gpiox_Idr) (X=A..g
172
Port Output Data Register (Gpiox_Odr) (X=A
173
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A
173
Port Bit Reset Register (Gpiox_Brr) (X=A
174
Port Configuration Lock Register (Gpiox_Lckr) (X=A
174
Alternate Function I/O and Debug Configuration (AFIO)
175
Using OSC32_IN/OSC32_OUT Pins as GPIO Ports PC14/PC15
175
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD1
175
CAN1 Alternate Function Remapping
176
CAN2 Alternate Function Remapping
176
JTAG/SWD Alternate Function Remapping
176
Table 34. CAN1 Alternate Function Remapping
176
Table 35. CAN2 Alternate Function Remapping
176
Table 36. Debug Interface Signals
176
ADC Alternate Function Remapping
177
Table 37. Debug Port Mapping
177
Table 38. ADC1 External Trigger Injected Conversion Alternate Function Remapping
177
Table 39. ADC1 External Trigger Regular Conversion Alternate Function Remapping
177
Table 40. ADC2 External Trigger Injected Conversion Alternate Function Remapping
177
Timer Alternate Function Remapping
178
Table 41. ADC2 External Trigger Regular Conversion Alternate Function Remapping
178
Table 42. TIM5 Alternate Function Remapping
178
Table 43. TIM4 Alternate Function Remapping
178
Table 44. TIM3 Alternate Function Remapping
178
Table 45. TIM2 Alternate Function Remapping
179
Table 46. TIM1 Alternate Function Remapping
179
Table 47. TIM9 Remapping
179
Table 48. TIM10 Remapping
179
USART Alternate Function Remapping
180
Table 49. TIM11 Remapping
180
Table 50. TIM13 Remapping
180
Table 51. TIM14 Remapping
180
Table 52. USART3 Remapping
180
Table 53. USART2 Remapping
180
I2C1 Alternate Function Remapping
181
SPI1 Alternate Function Remapping
181
SPI3/I2S3 Alternate Function Remapping
181
Ethernet Alternate Function Remapping
181
Table 54. USART1 Remapping
181
Table 55. I2C1 Remapping
181
Table 56. SPI1 Remapping
181
Table 57. SPI3/I2S3 Remapping
181
Table 58. ETH Remapping
182
AFIO Registers
183
Event Control Register (AFIO_EVCR)
183
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)
184
External Interrupt Configuration Register 1 (AFIO_EXTICR1)
191
External Interrupt Configuration Register 2 (AFIO_EXTICR2)
191
External Interrupt Configuration Register 3 (AFIO_EXTICR3)
192
External Interrupt Configuration Register 4 (AFIO_EXTICR4)
192
AF Remap and Debug I/O Configuration Register2 (AFIO_MAPR2)
193
GPIO and AFIO Register Maps
194
Table 59. GPIO Register Map and Reset Values
194
Table 60. AFIO Register Map and Reset Values
194
Interrupts and Events
196
Nested Vectored Interrupt Controller (NVIC)
196
Systick Calibration Value Register
196
Interrupt and Exception Vectors
197
Table 61. Vector Table for Connectivity Line Devices
197
Table 62. Vector Table for XL-Density Devices
200
Table 63. Vector Table for Other Stm32F10Xxx Devices
203
External Interrupt/Event Controller (EXTI)
205
Main Features
206
Block Diagram
206
Wakeup Event Management
206
Figure 20. External Interrupt/Event Controller Block Diagram
206
Functional Description
207
External Interrupt/Event Line Mapping
208
Figure 21. External Interrupt/Event GPIO Mapping
208
EXTI Registers
210
Interrupt Mask Register (EXTI_IMR)
210
Event Mask Register (EXTI_EMR)
210
Rising Trigger Selection Register (EXTI_RTSR)
211
Falling Trigger Selection Register (EXTI_FTSR)
211
Software Interrupt Event Register (EXTI_SWIER)
212
Pending Register (EXTI_PR)
212
EXTI Register Map
213
Table 64. External Interrupt/Event Controller Register Map and Reset Values
213
Analog-To-Digital Converter (ADC)
214
ADC Introduction
214
ADC Main Features
215
ADC Functional Description
215
Figure 22. Single ADC Block Diagram
216
Table 65. ADC Pins
217
ADC Clock
218
ADC On-Off Control
218
Channel Selection
218
Single Conversion Mode
218
Continuous Conversion Mode
219
Figure 23. Timing Diagram
219
Timing Diagram
219
Analog Watchdog
220
Figure 24. Analog Watchdog Guarded Area
220
Scan Mode
220
Table 66. Analog Watchdog Channel Selection
220
Figure 25. Injected Conversion Latency
221
Injected Channel Management
221
Discontinuous Mode
222
Calibration
222
Data Alignment
223
Figure 26. Calibration Timing Diagram
223
Figure 27. Right Alignment of Data
223
Figure 28. Left Alignment of Data
223
Channel-By-Channel Programmable Sample Time
224
Conversion on External Trigger
224
Table 67. External Trigger for Regular Channels for ADC1 and ADC2
224
Table 68. External Trigger for Injected Channels for ADC1 and ADC2
225
Table 69. External Trigger for Regular Channels for ADC3
225
Table 70. External Trigger for Injected Channels for ADC3
225
DMA Request
226
Dual ADC Mode
227
Figure 29. Dual ADC Block Diagram
228
Figure 30. Injected Simultaneous Mode on 4 Channels
229
Injected Simultaneous Mode
229
Regular Simultaneous Mode
229
Fast Interleaved Mode
230
Figure 31. Regular Simultaneous Mode on 16 Channels
230
Figure 32. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode
230
Slow Interleaved Mode
230
Alternate Trigger Mode
231
Figure 33. Slow Interleaved Mode on 1 Channel
231
Figure 34. Alternate Trigger: Injected Channel Group of each ADC
231
Combined Regular Simultaneous + Alternate Trigger Mode
232
Combined Regular/Injected Simultaneous Mode
232
Figure 35. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model
232
Independent Mode
232
Combined Injected Simultaneous + Interleaved
233
Figure 36. Alternate + Regular Simultaneous
233
Figure 37. Case of Trigger Occurring During Injected Conversion
233
Figure 38. Interleaved Single Channel with Injected Sequence CH11, CH12
233
Temperature Sensor
234
Figure 39. Temperature Sensor and VREFINT Channel Block Diagram
234
ADC Interrupts
235
Table 71. ADC Interrupts
235
ADC Registers
236
ADC Status Register (ADC_SR)
236
ADC Control Register 1 (ADC_CR1)
237
ADC Control Register 2 (ADC_CR2)
239
ADC Sample Time Register 1 (ADC_SMPR1)
243
ADC Sample Time Register 2 (ADC_SMPR2)
244
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
244
ADC Watchdog High Threshold Register (ADC_HTR)
245
ADC Watchdog Low Threshold Register (ADC_LTR)
245
ADC Regular Sequence Register 1 (ADC_SQR1)
246
ADC Regular Sequence Register 2 (ADC_SQR2)
247
ADC Regular Sequence Register 3 (ADC_SQR3)
248
ADC Injected Sequence Register (ADC_JSQR)
249
ADC Injected Data Register X (Adc_Jdrx) (X= 1
250
ADC Regular Data Register (ADC_DR)
250
11.12.15 ADC Register Map
251
Table 72. ADC Register Map and Reset Values
251
Digital-To-Analog Converter (DAC)
253
DAC Introduction
253
DAC Main Features
253
Table 73. DAC Pins
254
Figure 40. DAC Channel Block Diagram
254
DAC Functional Description
255
DAC Channel Enable
255
DAC Output Buffer Enable
255
DAC Data Format
255
DAC Conversion
256
Figure 41. Data Registers in Single DAC Channel Mode
256
Figure 42. Data Registers in Dual DAC Channel Mode
256
DAC Output Voltage
257
DAC Trigger Selection
257
Table 74. External Triggers
257
Figure 43. Timing Diagram for Conversion with Trigger Disabled TEN = 0
257
DMA Request
258
Noise Generation
258
Figure 44. DAC LFSR Register Calculation Algorithm
258
Triangle-Wave Generation
259
Figure 45. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
259
Figure 46. DAC Triangle Wave Generation
259
Dual DAC Channel Conversion
260
Independent Trigger Without Wave Generation
260
Figure 47. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
260
Independent Trigger with same LFSR Generation
261
Independent Trigger with Different LFSR Generation
261
Independent Trigger with same Triangle Generation
261
Independent Trigger with Different Triangle Generation
262
Simultaneous Software Start
262
Simultaneous Trigger Without Wave Generation
262
Simultaneous Trigger with same LFSR Generation
263
Simultaneous Trigger with Different LFSR Generation
263
Simultaneous Trigger with same Triangle Generation
263
Simultaneous Trigger with Different Triangle Generation
264
DAC Registers
264
DAC Control Register (DAC_CR)
264
DAC Software Trigger Register (DAC_SWTRIGR)
267
DAC Channel1 12-Bit Right-Aligned Data Holding Register
268
(Dac_Dhr12R1)
268
DAC Channel1 12-Bit Left Aligned Data Holding Register
268
(Dac_Dhr12L1)
268
DAC Channel1 8-Bit Right Aligned Data Holding Register
268
(Dac_Dhr8R1)
268
DAC Channel2 12-Bit Right Aligned Data Holding Register
269
(Dac_Dhr12R2)
269
DAC Channel2 12-Bit Left Aligned Data Holding Register
269
(Dac_Dhr12L2)
269
DAC Channel2 8-Bit Right-Aligned Data Holding Register
269
(Dac_Dhr8R2)
269
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
270
DUAL DAC 12-Bit Left Aligned Data Holding Register
270
(Dac_Dhr12Ld)
270
DUAL DAC 8-Bit Right Aligned Data Holding Register
271
(Dac_Dhr8Rd)
271
DAC Channel1 Data Output Register (DAC_DOR1)
271
DAC Channel2 Data Output Register (DAC_DOR2)
271
DAC Register Map
272
Table 75. DAC Register Map
272
Direct Memory Access Controller (DMA)
273
DMA Introduction
273
DMA Main Features
273
Figure 48. DMA Block Diagram in Connectivity Line Devices
274
DMA Functional Description
275
DMA Transactions
275
Figure 49. DMA Block Diagram in Low-, Medium- High- and XL-Density Devices
275
Arbiter
276
DMA Channels
276
Programmable Data Width, Data Alignment and Endians
278
Table 76. Programmable Data Width & Endian Behavior (When Bits PINC = MINC = 1)
278
Error Management
279
Interrupts
280
DMA Request Mapping
280
Table 77. DMA Interrupt Requests
280
Figure 50. DMA1 Request Mapping
280
Table 78. Summary of DMA1 Requests for each Channel
282
Table 79. Summary of DMA2 Requests for each Channel
283
Figure 51. DMA2 Request Mapping
283
DMA Registers
284
DMA Interrupt Status Register (DMA_ISR)
284
DMA Interrupt Flag Clear Register (DMA
285
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1
286
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
287
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1
288
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
288
DMA Register Map
289
Table 80. DMA Register Map and Reset Values
289
Advanced-Control Timers (TIM1&TIM8)
292
TIM1&TIM8 Introduction
292
TIM1&TIM8 Main Features
293
Figure 52. Advanced-Control Timer Block Diagram
294
TIM1&TIM8 Functional Description
295
Time-Base Unit
295
Counter Modes
296
Figure 53. Counter Timing Diagram with Prescaler Division Change from 1 to 2
296
Figure 54. Counter Timing Diagram with Prescaler Division Change from 1 to 4
296
Figure 55. Counter Timing Diagram, Internal Clock Divided by 1
297
Figure 56. Counter Timing Diagram, Internal Clock Divided by 2
297
Figure 57. Counter Timing Diagram, Internal Clock Divided by 4
298
Figure 58. Counter Timing Diagram, Internal Clock Divided by N
298
Figure 59. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
298
Figure 60. Counter Timing Diagram, Update Event When ARPE=1
299
Figure 61. Counter Timing Diagram, Internal Clock Divided by 1
300
Figure 62. Counter Timing Diagram, Internal Clock Divided by 2
300
Figure 63. Counter Timing Diagram, Internal Clock Divided by 4
300
Figure 64. Counter Timing Diagram, Internal Clock Divided by N
301
Figure 65. Counter Timing Diagram, Update Event When Repetition Counter
301
Figure 66. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
302
Figure 67. Counter Timing Diagram, Internal Clock Divided by 2
303
Figure 68. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
303
Figure 69. Counter Timing Diagram, Internal Clock Divided by N
303
Repetition Counter
304
Figure 70. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
304
Figure 71. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
304
Figure 72. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
305
Clock Selection
306
Figure 73. Control Circuit in Normal Mode, Internal Clock Divided by 1
306
Figure 74. TI2 External Clock Connection Example
306
Figure 75. Control Circuit in External Clock Mode 1
307
Figure 76. External Trigger Input Block
307
Capture/Compare Channels
308
Figure 77. Control Circuit in External Clock Mode 2
308
Figure 78. Capture/Compare Channel (Example: Channel 1 Input Stage)
309
Figure 79. Capture/Compare Channel 1 Main Circuit
309
Input Capture Mode
310
Figure 80. Output Stage of Capture/Compare Channel (Channel 1 to 3)
310
Figure 81. Output Stage of Capture/Compare Channel (Channel 4)
310
PWM Input Mode
311
Forced Output Mode
312
Figure 82. PWM Input Mode Timing
312
Output Compare Mode
313
PWM Mode
314
Figure 83. Output Compare Mode, Toggle on OC1
314
Figure 84. Edge-Aligned PWM Waveforms (ARR=8)
315
Figure 85. Center-Aligned PWM Waveforms (ARR=8)
316
Complementary Outputs and Dead-Time Insertion
317
Figure 86. Complementary Output with Dead-Time Insertion
317
Figure 87. Dead-Time Waveforms with Delay Greater than the Negative Pulse
317
Using the Break Function
318
Figure 88. Dead-Time Waveforms with Delay Greater than the Positive Pulse
318
Figure 89. Output Behavior in Response to a Break
320
Clearing the Ocxref Signal on an External Event
321
Figure 90. Clearing Timx Ocxref
321
6-Step PWM Generation
322
Figure 91. 6-Step Generation, COM Example (OSSR=1)
322
One-Pulse Mode
323
Figure 92. Example of One Pulse Mode
323
Encoder Interface Mode
324
Table 81. Counting Direction Versus Encoder Signals
325
Timer Input XOR Function
326
Figure 93. Example of Counter Operation in Encoder Interface Mode
326
Figure 94. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
326
Interfacing with Hall Sensors
327
Figure 95. Example of Hall Sensor Interface
328
Timx and External Trigger Synchronization
329
Figure 96. Control Circuit in Reset Mode
329
Figure 97. Control Circuit in Gated Mode
330
Figure 98. Control Circuit in Trigger Mode
331
Timer Synchronization
332
Debug Mode
332
Figure 99. Control Circuit in External Clock Mode 2 + Trigger Mode
332
TIM1&TIM8 Registers
333
TIM1&TIM8 Control Register 1 (Timx_Cr1)
333
TIM1&TIM8 Control Register 2 (Timx_Cr2)
334
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
337
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
339
Table 82. Timx Internal Trigger Connection
339
TIM1&TIM8 Status Register (Timx_Sr)
341
TIM1&TIM8 Event Generation Register (Timx_Egr)
342
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
344
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
347
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
348
Table 83. Output Control Bits for Complementary Ocx and Ocxn Channels with
350
Break Feature
350
TIM1&TIM8 Counter (Timx_Cnt)
351
TIM1&TIM8 Prescaler (Timx_Psc)
351
TIM1&TIM8 Auto-Reload Register (Timx_Arr)
351
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
352
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)
352
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
353
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)
353
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
354
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)
354
TIM1&TIM8 DMA Control Register (Timx_Dcr)
356
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
357
TIM1&TIM8 Register Map
358
Table 84. TIM1&TIM8 Register Map and Reset Values
358
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ST STM32F102 series Reference Manual (690 pages)
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Microcontrollers
| Size: 11 MB
Table of Contents
Table of Contents
2
Documentation Conventions
32
List of Abbreviations for Registers
32
Glossary
32
Peripheral Availability
32
Memory and Bus Architecture
33
System Architecture
33
Figure 1. System Architecture
33
Memory Organization
34
Memory Map
35
Figure 2. Memory Map
35
Peripheral Memory Map
36
Table 1. Register Boundary Addresses
36
Bit Banding
38
Embedded SRAM
38
Embedded Flash Memory
39
Table 2. Flash Module Organization (Low-Density Devices)
39
Table 3. Flash Module Organization (Medium-Density Devices)
40
Table 4. Flash Module Organization (High-Density Devices)
41
Boot Configuration
43
Table 5. Boot Modes
43
CRC Calculation Unit
44
Introduction
44
CRC Main Features
44
Figure 3. CRC Calculation Unit Block Diagram
44
CRC Functional Description
45
CRC Registers
45
Data Register (CRC_DR)
45
Independent Data Register (CRC_IDR)
46
Control Register (CRC_CR)
46
CRC Register Map
47
Table 6. CRC Calculation Unit Register Map and Reset Values
47
Power Control (PWR)
48
Power Supplies
48
Figure 4. Power Supply Overview
48
Battery Backup Domain
49
Independent A/D Converter Supply and Reference Voltage
49
Voltage Regulator
50
Power Supply Supervisor
50
Power on Reset (Por)/Power down Reset (PDR)
50
Programmable Voltage Detector (PVD)
51
Figure 5. Power on Reset/Power down Reset Waveform
51
Figure 6. PVD Thresholds
51
Low-Power Modes
52
Slowing down System Clocks
52
Table 7. Low-Power Mode Summary
52
Peripheral Clock Gating
53
Sleep Mode
53
Table 8. Sleep-Now
53
Stop Mode
54
Table 9. Sleep-On-Exit
54
Standby Mode
55
Table 10. Stop Mode
55
Table 11. Standby Mode
56
Auto-Wakeup (AWU) from Low-Power Mode
57
Power Control Registers
57
Power Control Register (PWR_CR)
57
Power Control/Status Register (PWR_CSR)
59
PWR Register Map
60
Table 12. PWR - Register Map and Reset Values
60
Backup Registers (BKP)
61
BKP Introduction
61
BKP Main Features
61
BKP Functional Description
62
Tamper Detection
62
RTC Calibration
62
BKP Registers
63
Backup Data Register X (Bkp_Drx) (X = 1
63
RTC Clock Calibration Register (BKP_RTCCR)
63
Backup Control Register (BKP_CR)
64
Backup Control/Status Register (BKP_CSR)
65
BKP Register Map
66
Table 13. BKP - Register Map and Reset Values
66
Reset and Clock Control (RCC)
69
Reset
69
System Reset
69
Power Reset
70
Backup Domain Reset
70
Clocks
70
Figure 7. Reset Circuit
70
Figure 8. Clock Tree
71
Figure 9. HSE/ LSE Clock Sources
72
HSE Clock
72
HSI Clock
73
Pll
73
LSE Clock
74
LSI Clock
74
Clock Security System (CSS)
75
RTC Clock
75
System Clock (SYSCLK) Selection
75
Clock-Out Capability
76
Watchdog Clock
76
RCC Registers
77
Clock Control Register (RCC_CR)
77
Clock Configuration Register (RCC_CFGR)
78
Clock Interrupt Register (RCC_CIR)
81
APB2 Peripheral Reset Register (RCC_APB2RSTR)
83
APB1 Peripheral Reset Register (RCC_APB1RSTR)
85
AHB Peripheral Clock Enable Register (RCC_AHBENR)
87
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
88
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
90
Backup Domain Control Register (RCC_BDCR)
93
Control/Status Register (RCC_CSR)
94
RCC Register Map
96
Table 14. RCC - Register Map and Reset Values
96
General-Purpose and Alternate-Function I/Os (Gpios and Afios)
97
GPIO Functional Description
97
Figure 10. Basic Structure of a Standard I/O Port Bit
98
Figure 11. Basic Structure of a Five-Volt Tolerant I/O Port Bit
98
Atomic Bit Set or Reset
99
General-Purpose I/O (GPIO)
99
Table 16. Output MODE Bits
99
Alternate Functions (AF)
100
External Interrupt/Wakeup Lines
100
GPIO Locking Mechanism
100
Software Remapping of I/O Alternate Functions
100
Figure 12. Input Floating/Pull Up/Pull down Configurations
101
Input Configuration
101
Output Configuration
101
Alternate Function Configuration
102
Figure 13. Output Configuration
102
Analog Input Configuration
103
Figure 14. Alternate Function Configuration
103
Figure 15. High Impedance-Analog Input Configuration
104
GPIO Registers
105
Port Configuration Register Low (Gpiox_Crl) (X=A..g
105
Table 15. Port Bit Configuration Table
105
Port Configuration Register High (Gpiox_Crh) (X=A..g
106
Port Input Data Register (Gpiox_Idr) (X=A..g
107
Port Output Data Register (Gpiox_Odr) (X=A..g
107
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A..g
108
Port Bit Reset Register (Gpiox_Brr) (X=A..g
108
Port Configuration Lock Register (Gpiox_Lckr) (X=A..g
109
Alternate Function I/O and Debug Configuration (AFIO)
110
Using OSC32_IN/OSC32_OUT Pins as GPIO Ports PC14/PC15
110
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD1
110
BXCAN Alternate Function Remapping
110
JTAG/SWD Alternate Function Remapping
110
Table 17. BXCAN Alternate Function Remapping
110
Table 18. Debug Interface Signals
111
Table 19. Debug Port Mapping
111
ADC Alternate Function Remapping
112
Timer Alternate Function Remapping
112
Table 20. ADC1 External Trigger Injected Conversion Alternate Function Remapping
112
Table 21. ADC1 External Trigger Regular Conversion Alternate Function Remapping
112
Table 22. ADC2 External Trigger Injected Conversion Alternate Function Remapping
112
Table 23. ADC2 External Trigger Regular Conversion Alternate Function Remapping
112
Table 24. Timer 5 Alternate Function Remapping
112
Table 25. Timer 4 Alternate Function Remapping
113
Table 26. Timer 3 Alternate Function Remapping
113
Table 27. Timer 2 Alternate Function Remapping
113
USART Alternate Function Remapping
114
Table 28. Timer 1 Alternate Function Remapping
114
Table 29. USART3 Remapping
114
Table 30. USART2 Remapping
114
I2C 1 Alternate Function Remapping
115
SPI 1 Alternate Function Remapping
115
AFIO Registers
115
Table 31. USART1 Remapping
115
Table 32. I2C1 Remapping
115
Table 33. SPI1 Remapping
115
Event Control Register (AFIO_EVCR)
116
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)
117
External Interrupt Configuration Register 1 (AFIO_EXTICR1)
119
External Interrupt Configuration Register 2 (AFIO_EXTICR2)
120
External Interrupt Configuration Register 3 (AFIO_EXTICR3)
120
External Interrupt Configuration Register 4 (AFIO_EXTICR4)
121
GPIO and AFIO Register Maps
121
Table 34. GPIO Register Map and Reset Values
121
Table 35. AFIO Register Map and Reset Values
122
Interrupts and Events
123
Nested Vectored Interrupt Controller (NVIC)
123
Systick Calibration Value Register
123
Interrupt and Exception Vectors
123
Table 36. Vector Table
124
External Interrupt/Event Controller (EXTI)
126
Main Features
126
Block Diagram
126
Wakeup Event Management
127
Functional Description
127
Figure 16. External Interrupt/Event Controller Block Diagram
127
External Interrupt/Event Line Mapping
128
Figure 17. External Interrupt/Event GPIO Mapping
129
EXTI Registers
130
Interrupt Mask Register (EXTI_IMR)
130
Event Mask Register (EXTI_EMR)
130
Rising Trigger Selection Register (EXTI_RTSR)
131
Falling Trigger Selection Register (EXTI_FTSR)
131
Software Interrupt Event Register (EXTI_SWIER)
132
Pending Register (EXTI_PR)
132
EXTI Register Map
133
Table 37. External Interrupt/Event Controller Register Map and Reset Values
133
DMA Controller (DMA)
134
Introduction
134
DMA Main Features
134
DMA Functional Description
135
DMA Transactions
135
Figure 18. DMA Block Diagram
135
Arbiter
136
DMA Channels
136
Error Management
137
Interrupts
138
DMA Request Mapping
138
Table 38. DMA Interrupt Requests
138
Figure 19. DMA1 Request Mapping
139
Table 39. Summary of DMA1 Requests for each Channel
140
Table 40. Summary of DMA2 Requests for each Channel
141
Figure 20. DMA2 Request Mapping
141
DMA Registers
142
DMA Interrupt Status Register (DMA_ISR)
142
DMA Interrupt Flag Clear Register (DMA
143
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1
144
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
145
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1
146
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
146
DMA Register Map
146
Table 41. DMA - Register Map and Reset Values
146
Analog-To-Digital Converter (ADC)
149
Introduction
149
ADC Main Features
149
ADC Functional Description
150
Figure 21. Single ADC Block Diagram
150
ADC Clock
151
ADC On-Off Control
151
Channel Selection
151
Table 42. ADC Pins
151
Continuous Conversion Mode
152
Single Conversion Mode
152
Timing Diagram
152
Analog Watchdog
153
Figure 22. Timing Diagram
153
Figure 23. Analog Watchdog Guarded Area
153
Table 43. Analog Watchdog Channel Selection
153
Injected Channel Management
154
Scan Mode
154
Discontinuous Mode
155
Figure 24. Injected Conversion Latency
155
Calibration
156
Data Alignment
156
Figure 25. Calibration Timing Diagram
156
Channel-By-Channel Programmable Sample Time
157
Conversion on External Trigger
157
Figure 26. Right Alignment of Data
157
Figure 27. Left Alignment of Data
157
Table 44. External Trigger for Regular Channels for ADC1 and ADC2
158
Table 45. External Trigger for Injected Channels for ADC1 and ADC2
158
DMA Request
159
Table 46. External Trigger for Regular Channels for ADC3
159
Table 47. External Trigger for Injected Channels for ADC3
159
Dual ADC Mode
160
Figure 28. Dual ADC Block Diagram
161
Figure 29. Injected Simultaneous Mode on 4 Channels
162
Injected Simultaneous Mode
162
Regular Simultaneous Mode
162
Fast Interleaved Mode
163
Figure 30. Regular Simultaneous Mode on 16 Channels
163
Figure 31. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode
163
Slow Interleaved Mode
163
Alternate Trigger Mode
164
Figure 32. Slow Interleaved Mode on 1 Channel
164
Figure 33. Alternate Trigger: Injected Channel Group of each ADC
164
Combined Regular Simultaneous + Alternate Trigger Mode
165
Combined Regular/Injected Simultaneous Mode
165
Figure 34. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model
165
Independent Mode
165
Combined Injected Simultaneous + Interleaved
166
Figure 35. Alternate + Regular Simultaneous
166
Figure 36. Case of Trigger Occurring During Injected Conversion
166
Figure 37. Interleaved Single Channel with Injected Sequence CH11, CH12
166
Temperature Sensor
167
Figure 38. Temperature Sensor and VREFINT Channel Block Diagram
167
ADC Interrupts
168
Table 48. ADC Interrupts
168
ADC Registers
169
ADC Status Register (ADC_SR)
169
ADC Control Register 1 (ADC_CR1)
170
ADC Control Register 2 (ADC_CR2)
172
ADC Sample Time Register 1 (ADC_SMPR1)
175
ADC Sample Time Register 2 (ADC_SMPR2)
176
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
176
ADC Watchdog High Threshold Register (ADC_HTR)
177
ADC Watchdog Low Threshold Register (ADC_LTR)
177
ADC Regular Sequence Register 1 (ADC_SQR1)
178
ADC Regular Sequence Register 2 (ADC_SQR2)
178
ADC Regular Sequence Register 3 (ADC_SQR3)
179
ADC Injected Sequence Register (ADC_JSQR)
180
ADC Injected Data Register X (Adc_Jdrx) (X= 1
181
ADC Regular Data Register (ADC_DR)
181
10.12.15 ADC Register Map
182
Table 49. ADC - Register Map and Reset Values
182
Digital-To-Analog Converter (DAC)
184
Introduction
184
DAC Main Features
184
Table 50. DAC Pins
185
Figure 39. DAC Channel Block Diagram
185
DAC Functional Description
186
DAC Channel Enable
186
DAC Output Buffer Enable
186
DAC Data Format
186
DAC Conversion
187
Figure 40. Data Registers in Single DAC Channel Mode
187
Figure 41. Data Registers in Dual DAC Channel Mode
187
DAC Output Voltage
188
DAC Trigger Selection
188
Table 51. External Triggers
188
Figure 42. Timing Diagram for Conversion with Trigger Disabled TEN = 0
188
DMA Request
189
Noise Generation
189
Figure 43. DAC LFSR Register Calculation Algorithm
189
Triangle-Wave Generation
190
Figure 44. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
190
Figure 45. DAC Triangle Wave Generation
190
Dual DAC Channel Conversion
191
Independent Trigger Without Wave Generation
191
Figure 46. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
191
Independent Trigger with same LFSR Generation
192
Independent Trigger with Different LFSR Generation
192
Independent Trigger with same Triangle Generation
192
Independent Trigger with Different Triangle Generation
193
Simultaneous Software Start
193
Simultaneous Trigger Without Wave Generation
193
Simultaneous Trigger with same LFSR Generation
194
Simultaneous Trigger with Different LFSR Generation
194
Simultaneous Trigger with same Triangle Generation
194
Simultaneous Trigger with Different Triangle Generation
195
DAC Registers
196
DAC Control Register (DAC_CR)
196
DAC Software Trigger Register (DAC_SWTRIGR)
199
DAC Channel1 12-Bit Right-Aligned Data Holding Register
199
(Dac_Dhr12R1)
199
DAC Channel1 12-Bit Left Aligned Data Holding Register
200
(Dac_Dhr12L1)
200
DAC Channel1 8-Bit Right Aligned Data Holding Register
200
(Dac_Dhr8R1)
200
DAC Channel2 12-Bit Right Aligned Data Holding Register
201
(Dac_Dhr12R2)
201
DAC Channel2 12-Bit Left Aligned Data Holding Register
201
(Dac_Dhr12L2)
201
DAC Channel2 8-Bit Right-Aligned Data Holding Register
202
(Dac_Dhr8R2)
202
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
202
DUAL DAC 12-Bit Left Aligned Data Holding Register
203
(Dac_Dhr12Ld)
203
DUAL DAC 8-Bit Right Aligned Data Holding Register
203
(Dac_Dhr8Rd)
203
DAC Channel1 Data Output Register (DAC_DOR1)
204
DAC Channel2 Data Output Register (DAC_DOR2)
204
DAC Register Map
205
Table 52. DAC Register Map
205
ST STM32F102 series Application Note (29 pages)
Brand:
ST
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Table of Contents
2
General Information
6
Power Supplies
7
Introduction
7
Independent A/D Converter Supply and Reference Voltage
7
Figure 1. Power Supply Overview
7
Battery Backup
8
Voltage Regulator
8
Power Supply Schemes
8
Reset and Power Supply Supervisor
9
Power on Reset (POR) / Power down Reset (PDR)
9
Figure 2. Power Supply Scheme
9
Figure 3. Power on Reset/Power down Reset Waveform
9
Programmable Voltage Detector (PVD)
10
System Reset
10
Figure 4. PVD Thresholds
10
Figure 5. Simplified Diagram of the Reset Circuit
11
Clocks
12
HSE OSC Clock
12
Figure 6. External Clock
12
Figure 7. Crystal/Ceramic Resonators
12
External Source (HSE Bypass)
13
External Crystal/Ceramic Resonator (HSE Crystal)
13
LSE OSC Clock
14
External Source (LSE Bypass)
14
External Crystal/Ceramic Resonator (LSE Crystal)
14
Figure 8. External Clock
14
Figure 9. Crystal/Ceramic Resonators
14
Clock Security System (CSS)
15
Boot Configuration
16
Boot Mode Selection
16
Boot Pin Connection
16
Table 2. Boot Modes
16
Figure 10. Boot Mode Selection Implementation Example
16
Embedded Boot Loader Mode
17
Debug Management
18
Introduction
18
SWJ Debug Port (Serial Wire and JTAG)
18
Pinout and Debug Port Pins
18
SWJ Debug Port Pins
18
Figure 11. Host-To-Board Connection
18
Flexible SWJ-DP Pin Assignment
19
Table 3. Debug Port Pin Assignment
19
Table 4. SWJ I/O Pin Availability
19
Internal Pull-Up and Pull-Down Resistors on JTAG Pins
20
SWJ Debug Port Connection with Standard JTAG Connector
20
Figure 12. JTAG Connector Implementation
20
Recommendations
21
Printed Circuit Board
21
Component Position
21
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