Table 39. Summary Of The Dma1 Requests For Each Channel - ST STM32L4x6 Reference Manual

RM0351

Table 39. Summary of the DMA1 requests for each channel

Request.
Channel 1
number
0 ADC1
1 -
2 -
3 -
4 TIM2_CH3
TIM17_CH1
5
TIM17_UP
6 TIM4_CH1
7 -
Channel 2 Channel 3
ADC2 ADC3
SPI1_RX SPI1_TX
USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX
I2C3_TX I2C3_RX
TIM16_CH1
TIM2_UP
TIM16_UP
TIM3_CH4
TIM3_CH3
TIM3_UP
TIM6_UP
-
DAC1
TIM1_CH1 TIM1_CH2
DocID024597 Rev 3
Direct memory access controller (DMA)
Channel 4 Channel 5
DFSDM0 DFSDM1
SPI2_RX SPI2_TX
I2C2_TX I2C2_RX
- TIM2_CH1
TIM7_UP.
QUADSPI
DAC2
TIM4_CH2 TIM4_CH3
TIM15_CH1
TIM1_CH4
TIM15_UP
TIM1_TRIG
TIM15_TRIG
TIM1_COM
TIM15_COM
Channel 6 Channel 7
DFSDM2 DFSDM3
SAI2_A SAI2_B
I2C1_TX I2C1_RX
TIM16_CH1 TIM2_CH2
TIM16_UP TIM2_CH4
TIM3_CH1 TIM17_CH1
TIM3_TRIG TIM17_UP
- TIM4_UP
TIM1_UP TIM1_CH3
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