Figure 295. Triggering Tim2 With Update Of Tim3; Figure 296. Triggering Tim2 With Enable Of Tim3 - ST STM32L4x6 Reference Manual

RM0351
1. Configure TIM3 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM3_CR2 register).
2. Configure the TIM3 period (TIM3_ARR registers).
3. Configure TIM2 to get the input trigger from TIM3 (TS=010 in the TIM2_SMCR
register).
4. Configure TIM2 in trigger mode (SMS=110 in TIM2_SMCR register).
5. Start TIM3 by writing '1 in the CEN bit (TIM3_CR1 register).
As in the previous example, you can initialize both counters before starting counting.
Figure 296
mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of TIM3 when its TI1 input rises, and the enable of TIM2
with the enable of TIM3. Refer to

Figure 295. Triggering TIM2 with update of TIM3

shows the behavior with the same configuration as in

Figure 296. Triggering TIM2 with Enable of TIM3

DocID024597 Rev 3
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Figure 292 for connections. To ensure the counters are
Figure 295 but in trigger
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