Table of Contents
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Embedded Flash memory (FLASH)
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0 KEYR: Flash key
3.7.4
Flash option key register (FLASH_OPTKEYR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0
3.7.5
Flash status register (FLASH_SR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
OPTV
RD
Res.
Res.
ERR
ERR
rc_w1
rc_w1
108/1693
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
The following values must be written consecutively to unlock the FLACH_CR
register allowing flash programming/erasing operations:
KEY1: 0x45670123
KEY2: 0xCDEF89AB
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
OPTKEYR: Option byte key
The following values must be written consecutively to unlock the FLACH_OPTR
register allowing option byte programming/erasing operations:
KEY1: 0x08192A3B
KEY2: 0x4C5D6E7F
28
27
26
25
Res.
Res.
Res.
12
11
10
9
FAST
Res.
Res.
ERR
rc_w1
24
23
22
KEYR[31:16]
w
w
w
8
7
6
KEYR[15:0]
w
w
w
24
23
22
OPTKEYR[31:16]
w
w
w
8
7
6
OPTKEYR[15:0]
w
w
w
24
23
22
Res.
Res.
Res.
8
7
6
MISS
PGS
SIZ
ERR
ERR
ERR
rc_w1
rc_w1
rc_w1
DocID024597 Rev 3
21
20
19
18
w
w
w
w
5
4
3
w
w
w
w
21
20
19
18
w
w
w
w
5
4
3
w
w
w
w
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
PGA
WRP
PROG
Res.
ERR
ERR
ERR
rc_w1
rc_w1
rc_w1
RM0351
17
16
w
w
2
1
0
w
w
17
16
w
w
2
1
0
w
w
17
16
Res.
BSY
r
2
1
0
OP
EOP
ERR
rc_w1
rc_w1
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