Table 150. Tim1 Register Map And Reset Values - ST STM32L4x6 Reference Manual

RM0351
Bit 1 BK2CMP1E: BRK2 COMP1 enable
This bit enables the COMP1 for the timer's BRK2 input. COMP1 output is 'ORed' with the
other BRK2 sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bit 0 BK2INE: BRK2 BKIN input enable
This bit enables the BKIN2 alternate function input for the timer's BRK2 input. BKIN2 input is
'ORed' with the other BRK2 sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Note: Refer to
26.4.30 TIM1 register map
TIM1 registers are mapped as 16-bit addressable registers as described in the table below:
Offset Register
TIM1_CR1
0x00
Reset value
TIM1_CR2
0x04
Reset value
TIM1_SMCR
0x08
Reset value
TIM1_DIER
0x0C
Reset value
TIM1_SR
0x10
Reset value
TIM1_EGR
0x14
Reset value
0: COMP1 input disabled
1: COMP1 input enabled
bits in TIMx_BDTR register).
0: BKIN2 input disabled
1: BKIN2 input enabled
bits in TIMx_BDTR register).
Figure 232: Break and Break2 circuitry

Table 150. TIM1 register map and reset values

MMS2[3:0]
0
overview.
0 0 0 0 0
0 0
0 0
DocID024597 Rev 3
Advanced-control timers (TIM1/TIM8)
CKD
[1:0]
0 0 0 0
0 0 0 0 0 0 0 0
ETP
S ETF[3:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0
CMS
[1:0]
0 0 0 0 0 0 0
MMS
[2:0]
0 0 0 0 0 0
TS[2:0] SMS[2:0]
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
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