Table of Contents
Advertisement
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ETRSEL[1:0]
Res.
Res.
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bits 16:14 ETRSEL[2:0]: ETR source selection
These bits select the ETR input source.
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 13:0 Reserved, must be kept at reset value.
27.4.22
TIM3 option register 2 (TIM3_OR2)
Address offset: 0x60
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ETRSEL[1:0]
Res.
Res.
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bits 16:14 ETRSEL[2:0]: ETR source selection
These bits select the ETR input source.
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 13:0 Reserved, must be kept at reset value.
926/1693
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
000: ETR legacy mode
001: COMP1 output connected to ETR input
010: COMP2 output connected to ETR input
Other: reserved
bits in TIMx_BDTR register).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
000: ETR legacy mode
001: COMP1 output connected to ETR input
Other: reserved
bits in TIMx_BDTR register).
DocID024597 Rev 3
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
Res.
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
Res.
RM0351
16
ETR
SEL2
rw
0
Res.
16
ETR
SEL2
rw
0
Res.
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32L4x6 and is the answer not in the manual?
Questions and answers