Tim1/Tim8 Capture/Compare Mode Register 3 (Timx_Ccmr3) - ST STM32L4x6 Reference Manual

RM0351
26.4.23

TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3)

Address offset: 0x54
Reset value: 0x0000 0000
Refer to the above CCMR1 register description. Channels 5 and 6 can only be configured in
output.
31 30 29
Res. Res. Res. Res.
15 14 13
OC6
OC6M[2:0]
CE
rw rw rw
Output compare mode
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 OC6M[3]: Output Compare 6 mode - bit 3
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 OC5M[3]: Output Compare 5 mode - bit 3
Bit 15 OC6CE: Output compare 6 clear enable
Bits 14:12 OC6M: Output compare 6 mode
Bit 11 OC6PE: Output compare 6 preload enable
Bit 10 OC6FE: Output compare 6 fast enable
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 OC5CE: Output compare 5 clear enable
Bits 6:4 OC5M: Output compare 5 mode
Bit 3 OC5PE: Output compare 5 preload enable
Bit 2 OC5FE: Output compare 5 fast enable
Bits 1:0 Reserved, must be kept at reset value.
26.4.24 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5)
Address offset: 0x58
Reset value: 0x0000 0000
31 30 29
GC5C3 GC5C2 GC5C1 Res.
rw rw rw
15 14 13
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
OC6
OC6FE Res.
PE
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
DocID024597 Rev 3
Advanced-control timers (TIM1/TIM8)
24 23 22
OC6M[3] Res. Res. Res.
rw
8 7 6
OC5
Res. OC5M[2:0]
CE.
rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
CCR5[15:0]
rw rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
OC5PE OC5FE
rw rw rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
Res. OC5M[3]
rw
1 0
Res. Res.
17 16
Res. Res.
1 0
rw rw
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