Figure 161. Vlcd Pin For 1/2 1/3 1/4 Bias - ST STM32L4x6 Reference Manual

RM0351
1. R : Low value resistor network. R
LN
The R
LN
register (see
The HD switch follows the rules described below:
• If the HD bit and the PON[2:0] bits in the LCD_FCR register are reset, then HD switch
is open.
•
If the HD bit in the LCD_FCR register is reset and the PON[2:0] bits in the LCD_FCR
are different from 00 then, the HD switch is closed during the number of pulses defined
in the PON[2:0] bits.
•
If HD bit in the LCD_FCR register is 1 then HD switch is always closed.
Buffered mode
When voltage output buffers are enabled by setting BUFEN bit in the LCD_CR register, LCD
driving capability is improved as buffers prevent the LCD capacitive loads from loading the
resistor bridge unacceptably and interfering with its voltage generation. As a result we
obtain more stable intermediate voltage levels thus improving RMS voltage applied to the
LCD pixels.

Figure 161. VLCD pin for 1/2 1/3 1/4 bias

divider can be always switched on using the HD bit in the LCD_FCR configuration
Section 22.6.2).
DocID024597 Rev 3
Liquid crystal display controller (LCD)
: High value resistor network.
HN
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