Timx Status Register (Timx_Sr) - ST STM32L4x6 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
27.4.5

TIMx status register (TIMx_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF
rc_w0
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture
mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input
when the slave mode controller is enabled in all modes but gated mode. It is set when
the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
Refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
Refer to CC1IF description
910/1693
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
0: Update interrupt disabled.
1: Update interrupt enabled.
12 11 10 9
rc_w0 rc_w0 rc_w0
8 7 6
Res. Res. TIF
rc_w0
DocID024597 Rev 3
5 4 3 2
Res. CC4IF CC3IF CC2IF
rc_w0 rc_w0 rc_w0
RM0351
1 0
CC1IF UIF
rc_w0 rc_w0