ST STM32L4x6 Reference Manual page 670

Liquid crystal display controller (LCD)
In case the internal step-up converter is used (capacitor C
•
Configure the VLCD pin as alternate function LCD in the GPIO_AFR register.
•
Wait for the external capacitor C
approximately 2 ms for C
•
Set voltage source to internal source by resetting VSEL bit in the LCD_CR register
•
Enable the LCD controller by setting LCDEN bit in the LCD_CR register
In case of LCD external power source is used:
•
Set voltage source to external source by setting VSEL bit in the LCD_CR register
•
Configure the VLCD pin as alternate function LCD in the GPIO_AFR register
• Enable the LCD controller by setting LCDEN bit in the LCD_CR register
LCD intermediate voltages
The LCD voltage generator generates up to three intermediate voltage levels (1/3 V
V or 1/4 V
LCD
only one voltage level (1/2 V
In case of 1/2 bias, one voltage level (1/2 V
In case of 1/3 bias, two intermediate voltage levels (1/3 V
•
node a is 1/3 V
•
node b is 2/3 V
In case of 1/4 bias, three intermediate voltage levels (1/4 V
generated
•
node a is 1/4 V
•
node b is 1/2 V
•
node c is 3/4 V
LCD drive selection
1. High drive and low drive resistive network
Internal resistor networks are used to generate all intermediate voltages (see
Actually, one with low value resistors (R
are respectively used to increase the current during transitions and to reduce power
consumption in static state.
The EN switch allows the following rules:
If LCDEN bit in the LCD_CR register is set, the EN switch is closed.
When clearing the LCDEN bit in the LCD_CR register, the EN switch is open at the end of
the even frame in order to avoid a medium voltage level different from 0 considering the
entire frame odd plus even.
The PON[2:0] (Pulse ON duration) bits in the LCD_FCR register configure the time during
which R
LN
the common and segment lines change. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need a longer drive time to
achieve satisfactory contrast.
670/1693
EXT
, 2/4 V , 3/4 V
LCD LCD
) between V
LCD
LCD
LCD
LCD
LCD
LCD
is enabled (see Figure
DocID024597 Rev 3
to be charged (C
EXT
= 1 μF)
) between V and V
LCD SS
and V
SS LCD
) is generated and node b voltage is 1/2 V
LCD
) and one with high value resistors (R
LN
153) through the HD (high drive) switch when the levels of
on VLCD pin is required):
EXT
connected to the VLCD pin,
EXT
in case of 1/3 (1/4) bias and
LCD
in case of 1/2 bias.
, 2/3 V ) are generated
LCD LCD
, 1/2 V and 3/4 V
LCD LCD
Figure
RM0351
, 2/3
LCD
LCD
) are
LCD
161).
) which
HN